Optimal FPGA Implementation of Unsigned Bit-Serial Division


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Abstract


In the present paper, we show that a slight modification to a well-known unsigned nonrestoring division algorithm leads to an optimal mapping of a bit-serial divider to FPGA hardware. Advantages of the proposed implementation are: minimal area occupancy, and no online delay (i.e. the MSB of the quotient is obtained right with the next clock cycle after input of the first bit of the operands). Synthesis results are presented for two different Xilinx families of FPGAs, and different operand widths up to 64 bits. These results show that the number of 4-input LUTs occupied by one such divider is at most equal to operand length, and that the maximum clocking frequency largely exceeds 100MHz in every case tested.
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Keywords


FPGA; Unsigned Division; Nonrestoring; Bit Serial

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References


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