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Implementation of High Performance Convolution Based on Novel Mux-Multiplier

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In this paper, a 6×6 bit convolution circuit is designed using a new binary multiplier based on 2-to-1 multiplexer (Mux-Multiplier). The proposed Mux-Multiplier circuit is designed so as X-bits are fed to one of the 2-to-1 multiplexer inputs, while the other multiplexer inputs are grounded to zero. The Y-group bits become the control selector for each of all the multiplexers. All the multiplexer outputs are summed together by an adder to achieve the correct result. The whole convolution circuit is designed, coded and successfully gate level simulated on Field Programmable Gate Array (FPGA) Cyclone IV platform. The achieved result of Mux-Multiplier and convolution circuits described that these results are exactly matched with the mathematically obtained results. The proposed designed circuit operates with 9.111 ns delay time. The presented designed circuit with these good specifications makes the convolution circuit suitable in a wide range of Digital Signal Processing (DSP) applications, telecommunication and electronic systems.
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DSP; HDL; Mux-Multiplier; Signal Processing

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