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FPGA Implementation of FIR Filter Design Based on Novel Vedic Multiplier

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In this paper, a novel Vedic multiplier based on binary coded decimal (BCD) technique is introduced. The results of multiplication of two 4-bit numbers are listed in columns in order to design the desired multiplier. The columns are minimized to the desired equations using Karnaugh map. The proposed Vedic multiplier circuit, D-flip flop registers and arithmetic unit (adders) are used to implement a finite impulse response (FIR) filter. The FIR filter circuit has been coded using Verilog hardware description language (HDL), simulated and verified using Modelsim 6.5 software. The achieved results have demonstrated that the maximum operating frequency of the proposed Vedic multiplier is up to 207 MHz in contrast with 117.88 MHz for similar designs. Further, the proposed multiplier circuits uses 128 combinational logic cells, which is less than similar circuits by up to 17%.
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FIR Filter; Vedic Multiplier; FPGA; Adder; HDL Code; BCD Decoder

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