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VHDL Design and FPGA Implementation of the SVPWM of a Three-phase Asynchronous Machine Powered by a Voltage Inverter

Elhabib Lotfi(1*), Mustapha Elharoussi(2), Elhassane Abdelmounim(3)

(1) ASTI Laboratory, FST Hassan I University in Settat, Morocco
(2) ASTI Laboratory, FST Hassan I University in Settat, Morocco
(3) ASTI Laboratory, FST Hassan I University in Settat, Morocco
(*) Corresponding author


DOI: https://doi.org/10.15866/iremos.v10i4.11944

Abstract


In this paper, we will focus on the VHDL design and the FPGA implementation In the Loop (HIL) of the space-vector Pulse with modulation technique (SVPWM) applied to the three-phase inverter ensuring the speed variation of an asynchronous machine .We will adopt a modular approach, by dividing the global entity into a set of elementary blocks designed and implemented separately. The obtained performances of the proposed architecture of the SVPWM are 1185 LUTs of complexity and 2 latency clock cycles. We have also realized a platform based on the Matlab / Simulink and DSP Builder co-simulation of the speed variation of an asynchronous machine using our architecture, the results obtained enable us to validate our SVPWM circuit.
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Keywords


SVPWM; FPGA In The Loop; Co-Simulation; VHDL; Asynchronous Machine; DSP Builder

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