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Modeling and Simulation of a new BIST Circuit with VHDL-AMS: Application for Loop Filter Testing

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In the RF and mixed signal IC design, Built in Self Test (BIST) technique is becoming an important issue that affects both the time-to-market and product cost of many modem electronic systems. In most cases, these systems are evaluated and designed with electrical stimulation method. The main problem of electrical simulation tools is that the extraction of the parameters associated with the performances of circuit and the design rules depend broadly on the intuition of the experts. To overcome this problem, an efficient methodology for top-down design, modeling, and simulation of complete BIST circuit to validate its proper function before moving on to transistor level implementation is presented in this paper. The described method is based in
behavioral modeling strategy using hardware description language VHDL-AMS. At behavioral level, the performances of circuits are optimized by modeling and simulation these performances parameters with a hardware description language without considering its transistor level implementation. Hence, methods and algorithms for modeling has been developed, for simulation, in order to decrease the total simulation time, validation of systems, and accelerate the production cycle of electronic devices. The proposed BIST schema based on modeling and simulation strategy is applied to test a loop filter. Extensive simulation study shows that the proposed BIST approach can efficiently detect the loop filter fault and tolerate this type of fault, and so offers high fault coverage of 100% for the fault detects.
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BIST (Built In Self Test) Circuit; Top-down Design; Modeling and Simulation Process; Behavioral Modeling; VHDL-AMS; Loop Filter; PLLs

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A. Doboli and R. Vemuri, .Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS. IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 11, pp. 1504 .1520, November 2003.

E. Christen and K. Bakalar, .VHDL-AMS. A hardware description language for analog and mixed-signal applications,. IEEE Transactions on Circuits and Systems, vol. 46, pp. 1263.1272, October 1999.

Frevert, R., Haase, J., Jancke, R., Knochel, U., Schwarz, P., Kakerow, R., Darianian, M., Modeling and Simulation for RF System Design, Electronic &Electrical Engineering Springer, p291, 2005.

Z. M. ASHARI AND A.N. NORDIN, Heoretical Modeling and Simulation of Phase Locked Loop (PLL) for clock data recovery (CDR), IIUM Engineering Journal, Vol. 12, No. 5, 2011: Special Issue -1 on Science and Ethics in Engineering

M. Sida, R. Ahola, and D. Wallner, Bluetooth transceiver design and simulation with VHDL-AMS,. IEEE Circuits and Devices Magazine, vol. 19, pp. 11.14, March 2003.

J. Ravatin, J. Oudinot, S. Scotti, A. Le-Clercq, and J. Lebrun. Full transceiver circuit simulation using VHDL-AMS, Journal of Microwave Engineering, pp. 29.33, May 2002.

Barraj, I., Trabelsi, H., Bouzid, G., Masmoudi, M., Modeling, design and simulation of low complexity IR-UWB transceiver for medical monitoring applications, (2014) International Review on Modelling and Simulations (IREMOS), 7 (2), pp. 331-340.

Mohandass, S., Umamaheswari, G., Modelling and simulation of interference cancellation receiver for MIMO multicarrier CDMA based cognitive radio, (2014) International Review on Modelling and Simulations (IREMOS), 7 (1), pp. 196-205.

U. Knochel, J. Hartung, and R. Kakerow, .Verification of the RF subsystem within wireless LAN system level simulation, Design, Automation and Test in Europe Conference, pp. 286.291, 2003.

Chun-Lung Hsu, Yiting Lai, and Shu-Wei Wang, Built-In Self-Test for Phase-Locked Loops, IEEE Transactions on Instrumentation and Measurement, Vol. 54, No, 3, June 2005

J. Ramesh and K.Gunavathi, A Novel Built-In Self-Test Architecture for CP-PLL. May, ICGST-PDCS Journal, Volume 7, Issue 1, May 2007.

Ashish Tiwari, Anil Kumar Sahu. Mixed signal IC (CP-PLL) Testing scheme using a novel approach. International Journal of Scientific & Engineering Research Volume 3, Issue 5, May-2012

Ashish Tiwari, Anil Kumar Sahu, G.R.Sinha. Design for Testability architecture using the existing elements of CP-PLL for digital testing applications in VLSI ASIC design. International Journal of VLSI & Signal Processing Applications, Vol.2,Issue 1, Feb 2012, (56-64).

Intissar Toihria, Rim Ayadi and Mohamed Masmoudi, ''Analysis of a Third-Order Charge-Pump Phase-Locked Loops used for Wireless Sensor Transceiver'', International Journal of Computer Applications, Vol.77, No.3, pp.36-41, September 2013.

Intissar Toihria, Rim Ayadi and Mohamed Masmoudi, ''High Performance BIST PLL Approach for VCO Testing'', International Conference on Advanced Technologies for Signal & Image Processing (ATSIP) Sousse-Tunisia, 17-19 March 2014.

F. M. Gardner, Charge-Pump Phase-Lock Loops, IEEE Trans. Communication, vol. COM-28, 1849–1858, Nov. 1980.

Intissar Toihria, Rim Ayadi and Mohamed Masmoudi, Design of an Effective Charge Pump-Phase Locked Loops Architecture for RF Applications, International Journal of Computer Applications, Volume 74– No.3, July 2013.

Pascal ACCO, Etude de la boucle à verrouillage de phase par impulsions de charge Prise en compte des aspects hybrides, Décembre 2003.

K. Holladay, Design a PLL for specific loop bandwidth, END EUROPE, pp 64-66, October 2000

Ahmed FAKHFAKH, Contribution à la modélisation comportementale des circuits radiofréquence, 11 Janvier 2002

Serge Dusausay, Comprendre l'électronique par la simulation.

S. Kim and M. Soma, "An all-digital built-in self-test for high-speed phase-locked loops," IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process, vol. 48, no. 2, pp. 141–150, Feb. 2001.

M. Soma, "Challenges in analog and mixed-signal fault models," IEEE Circuit Devices Mag., vol. 12, pp. 16–19, Jan. 1996.


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