On the Use of Pulse Height Modulation for Harmonic Cancellation in a Six-Level Inverter Topology

Sid-Ali Amamra(1*), Kamal Meghriche(2), Eric Monacelli(3), Abderrezzak Cherifi(4)

(1) Versailles Laboratory of Systems Engineering (LISV) University of Versailles Saint-Quentin-en-Yvelines (UVSQ), 10 avenue de l’Europe, 78140 Vélizy, France
(2) Versailles Laboratory of Systems Engineering (LISV) University of Versailles Saint-Quentin-en-Yvelines (UVSQ), 10 avenue de l’Europe, 78140 Vélizy, France
(3) Versailles Laboratory of Systems Engineering (LISV) University of Versailles Saint-Quentin-en-Yvelines (UVSQ), 10 avenue de l’Europe, 78140 Vélizy, France
(4) Versailles Laboratory of Systems Engineering (LISV) University of Versailles Saint-Quentin-en-Yvelines (UVSQ), 10 avenue de l’Europe, 78140 Vélizy, France
(*) Corresponding author


DOI's assignment:
the author of the article can submit here a request for assignment of a DOI number to this resource!
Cost of the service: euros 10,00 (for a DOI)

Abstract


This paper deals with harmonics cancellation using pulse height modulation (PHM). This technique allows simultaneous optimization of the total harmonic distortion (THD) rate and the number of power switches. This leads to substantial reduction of the power switching losses as compared with PWM. A novel six-level inverter model is presented with three-phase output voltages having similar symmetry properties to a pure three-phase sinusoidal system. The proposed method allows canceling all even-order harmonics and integer multiples of the third-order harmonic. Switching angles and input dc voltage levels are determined so as to cancel most of the successive low-order harmonics (the most harmful to the network) starting from rank 2, allowing to shift the first nonzero harmonic far away from the fundamental. For 12 switching states per period, PHM allows to cancel harmonics from rank 2 to 10 with lower THD. A comparative study of the obtained output voltage and current shows their compliance with IEEE 519-1992 and IEC 61000-3-12 standards.
Copyright © Praise Worthy Prize - All rights reserved.

Keywords


Pulse Heigh Modulation; Selective Harmonics Elimination; Six-Level Waveform; Fourier Analysis IEEE 519-1992; IEC 61000-3-12

Full Text:

PDF


References


Parlak, K.S., Özdemir, M., Aydemir, M.T., Elimination of voltage harmonics caused by nonlinear loads in distributed power systems consisting of inverters, (2009) International Review of Electrical Engineering (IREE), 4 (2), pp. 228-234.

Shojaei, A., Fathi, S.H., An improved Selective Harmonics Elimination method to reduce voltage THD in parallel multilevel inverters, (2011) International Review of Electrical Engineering (IREE), 6 (7), pp. 3196-3203.

Ebadpour, M., Sharifian, M.B.B., Cascade H-bridge multilevel inverter with low output harmonics for electric/hybrid electric vehicle applications, (2012) International Review of Electrical Engineering (IREE), 7 (1), pp. 3248-3256.

Laali, S., Abbaszadeh, K., Lesani, H., Control of asymmetric cascaded multilevel inverters based on charge balance control methods, (2011) International Review of Electrical Engineering (IREE), 6 (2), pp. 522-528.

Shahgholian, G., Faiz, J., Jabbari, M., Voltage control techniques in uninterruptible power supply inverters: A review, (2011) International Review of Electrical Engineering (IREE), 6 (4), pp. 1531-1542.

D. Ahmadi, K. Zou, C. Li, Y. Huang and J. Wang, A Universal Selective Harmonic Elimination Method for High-Power Inverters, IEEE Trans on Power Electronics, vol. 26, no. 10, October 2011, pp. 2743-2753.

R. Nagarajan, M. Saravanan, Comparison of PWM Control Techniques for Cascaded Multilevel Inverter, International Review of Automatic Contro (IRAC)l, vol.5, N.5. Sepember 2012.

H. Hakimollahi, S. H. Fathi, M. Jamshidi, J. S. Moghani, Elimination of Low Order Harmonics in a Cascaded H-Bridge Seven-Level Six-Phase Inverter with Adjustable DC Sources, International Review of Electrical Engineering (IREE), Vol. 6. n. 1, February 2011, pp. 109-116.

N. Farokhnia, H. Vadizadeh, F. Anvariasl, Line Voltage THD calculation of Cascaded Multilevel Inverter's Stepped Waveform with Equal DC Sources, International Review of Electrical Engineering (IREE), Vol. 6. n. 3, June 2011, pp. 1094-1108.

L. M. Tolbert, J. N. Chiasson, Z. Du, and K. J. McKenzie, Elimination of harmonics in a multilevel converter with non equal DC sources, IEEE Trans Industrial Applications, vol. 41, no. 1, February. 2005, pp. 75–82.

F. J. T. Filho, T. H. A. Mateus, H. Z. Maia, B. Ozpineci, J. O. P. Pinto, and L. M. Tolbert, Real-time selective harmonic minimization in cascaded multilevel inverters with varying DC sources, Proc IEEE Power Electron. Spec. Conf., Rhodes, Greece, Jun. 15–19, 2008, pp. 4302–4306.

J. N. Chiasson, L. M. Tolbert, K. J. McKenzie, and Z. Du, A unified approach to solving the harmonic elimination equations in multilevel converters, IEEE Trans. Power Electronics, vol. 19, no. 2, Mar. 2004, pp. 478–490.

J. Wang and D. Ahmadi, A precise and practical harmonic elimination method for multilevel inverters, IEEE Trans Industrial Applications, vol. 46, no. 2, March. 2010, pp. 857–865.

D. Ahmadi and J. Wang, Selective harmonic elimination for multilevel inverters with unbalanced DC inputs, in Proc. IEEE Veh. Power Propuls. Conf. (VPPC), Sepember. 2009, pp. 773–778.

D. Ahmadi and J. Wang, Weight oriented optimal PWM in low modulation indices for multilevel inverters with unbalanced DC sources, Proc. IEEE Appl. Power Electron. Conf. Expo. (APEC), Feb. 2010, pp. 1038– 1042.

Y. Liu, H. Hong, and A. Q. Huang, Real-time calculation of switching angles minimizing THD for multilevel inverters with Step modulation, IEEE Trans Industrial Electronics, vol. 56, no. 2, February. 2009, pp. 285–293.

J. N. Chiasson, L. M. Tolbert, Z. Du, and K. J. McKenzie, The use of power sums to solve the harmonic elimination equations for multilevel converters, European Power Electron and Drives, vol. 15, no. 1, February. 2005, pp. 19–27.

J. Pontt, J. Rodriguez, and R. Huerta, Mitigation of non-eliminated harmonics of SHEPWM three-level multi-pulse three-phase active front end converters with low switching frequency for meeting standard IEEE-519– 92, IEEE Transaction Power Electronics, vol. 19, no. 6, November. 2004, pp. 1594–1600.

M. S. A. Dahidah and V. G. Agelidis, Selective harmonic elimination PWM control for cascaded multilevel voltage source converters: A generalized formula, IEEE Trans Power Electronics, vol. 23, no. 4, July. 2008, pp. 1620– 1630.

IEEE Standard 519-1992. Recommended practices and requirements for harmonic control in electrical power systems. The institute of electrical and electronics engineers. 1993.

IEC Standard 61000-3-12. International Electrotechnical Commission, 2004.


Refbacks

  • There are currently no refbacks.



Please send any question about this web site to info@praiseworthyprize.com
Copyright © 2005-2021 Praise Worthy Prize