Hardware Implementations of AES Algorithm for 32-bit Embedded System


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Abstract


The performance evaluation of cryptographic algorithms has guided to serious studies of its implementations. The efficiency of these algorithms is improved by applying good design rules adapted to devices and to its resources constraints. In this paper, we present a careful study of three possible designs of the Advanced Encryption Standard (AES) targeting 32-bit embedded system; we examined AES implementations which use arithmetic properties of the AES S-box and structures based on hardware look-up tables. We have analyzed and compared different characteristics like clock frequency, occupancy area, and power consumption of these implementations. The resulting designs are implemented using Xilinx XC5VFX70t FPGA device and an ASIC CMOS 40 nm technology. Our results show that AES implementation based on hardware look-up table shows the lowest power consumption and highest frequency. The AES implementations which use arithmetic properties of the S-box are characterized by the smallest silicon area.
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Keywords


AES; SubByte Operation; 32-bit Platform; FPGA Implementation; ASIC Implementation; Embedded System

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References


National Institute of Standards and Technology (NIST). Advanced Encryption Standard (AES )Federal Information Processing Standards Publications (FIPS PUBS)197-26, (2001)

Gaisler website http://www.gaisler.com.

Arm website , http://www.arm.com.

STMicroelectronics website , www.st.com.

Khanob Thongkhome, Chalermwat Thanavijitpun, and Somsak Choomchuay,An implementaion of S-BOX for a compact AES system, ITC-CSCC 2010.

L.Thulasimani, M.Madheswaran ,A singel chip design an implementation of AES-128/192/256 encryption algorithm, International Journal of Engineering Science and Technology , vol. 2 n.5, pp 1052-1059, 2010.

Muhammad H. Rais and Syed M. Qasim, A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box, IJCSNS, vol. 9 n. 9, pp. 305-309, 2009.

C.Hocquet, D.Kamel, F.Regazzoni, J.D.Legat, D.Flandre, D.Bol, F.X.tandaert, Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags, Journal of Cryptographic Engineering, vol. 1 n. 1, 2011, pp. 79-86

S.Tillich, M. Feldhofer, and J.Großschadl, Area delay and power characteristics of standard-cell implementations of the AES S-Box, Journal of Signal Processing Systems; Volume 50 Issue 2, February 2008.

R. Lidl and H. Niederreiter. Finite Fields. Cambridge University Press, second edition, 772 pages, 1996.

Daemen and V. Rijmen. The Design of Rijndael. Springer Verlag, 238 pages, 2002.

D. Canright. A Very Compact S-Box for AES. In J. R. Rao and B. Sunar,editors, Cryptographic Hardware and Embedded Systems – CHES 2005, 7th International Workshop, Edinburgh, 2005, Proceedings, volume 3659 of Lecture Notes in Computer Science, pp 441–455. Springer, 2005.

Fan, C.-P., Hwang, J.-K., FPGA implementations of high throughput sequential and fully pipelined AES algorithm, (2008) International Journal of Electrical Engineering, 15 (6), pp. 447-455.

J. Wolkerstorfer, E. Oswald, and M. Lamberger. An ASIC implementation of the AES SBoxes. In B. Preneel, CT-RSA 2002, The Cryptographers’ Track at the RSA Conference 2002, SanJose, CA, USA, Proceedings, volume 2271 of Lecture Notes in Computer Science, pp 67–78. Springer, 2002.

Nedjah, L. de Macedo Mourelle, and M.P Cardoso. A Compact

Piplined Hardware Implementation of the AES128 Cipher. The

Third International Conference on Information Technology: New Generations, pp 216–221, 2006.

Somsak Choomchuay, Surapong Pongyupinpanich and Somsanouk Pathumvanh, A Compact 32-bit Architecture for an AES System, ECTI Transactions on computer and information theory, vol .1 n.1, 2005, pp 24-29.

N. Benhadjyoussef , W. Elhadjyoussef, M.Machhout and R. Tourki, A compact 32-bit AES design for embedded system, 2012 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2012).

Karami, B., Security-constrained unit commitment with considering demand response with high penetration of wind power, (2012) International Review on Modelling and Simulations (IREMOS), 5 (4), pp. 1717-1724.

Heidari, A., Mortazavi, S.S., Optimal operation of a distribution company in restructured power systems with voltage stability and reliability constraints, (2011) International Review on Modelling and Simulations (IREMOS), 4 (4), pp. 1709-1716.

Bastin Solai Nazaran, J., Selvi, K., Security enhanced optimal power flow with transmission cost solution, (2012) International Review of Electrical Engineering (IREE), 7 (4), pp. 4963-4970.


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