LUT Cascade-Based Architectures for High Productivity Embedded Systems

V. Dvorak(1*)

(1) Brno University of Technology, Faculty of Information Technology, Czech Republic
(*) Corresponding author


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Abstract


Fast, flexible, cheap in hardware or low-power implementations of multiple-output Boolean functions are often required in embedded systems. The paper describes digital system architectures which embody some of these attributes. They are based on already known, and recently reinvented, representation of combinational logic by Look-Up Table (LUT) cascades. Theoretical background of cascade decomposition is revised and a relation to decision diagrams is pinpointed. The design of LUT cascades is discussed and a heuristic method of cascade synthesis is given. Three possible applications of LUT cascades are presented: combinational logic pipelines, efficient micro-programs with multi-way branching and fast logic simulation in software. It is shown that LUT cascades are quite flexible in making trade-offs between performance and cost by adjusting cascade length, complexity of its cells and multiplicity of cascades. The method of LUT cascades may be quite useful not only for high performance pipelined stream processing or embedded microprocessor or microcontroller firmware, but also in digital system simulation.
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Keywords


LUT Cascades; Binary Decision Diagrams BDD; MTBDD; Iterative Disjunctive Decomposition; Multi-Way Branching

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References


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