A Computer Architecture Educational System Based on a 32-bit RISC Processor

D. Mandalidis(1*), P. Kenterlis(2), J. N. Ellinas(3)

(1) Department of Electronic Computer Systems, Technological Education Institute of Piraeus, Greece
(2) Department of Electronic Computer Systems, Technological Education Institute of Piraeus, Greece
(3) Department of Electronic Computer Systems, Technological Education Institute of Piraeus, Greece
(*) Corresponding author


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Abstract


This paper describes the implementation of a system-on-a-programmable-chip (SOPC) development board to support computer architecture laboratories at a low cost. A commercial field-programmable gate-array (FPGA) was employed to develop our reduced-instruction-set-computer (RISC) soft processor core that may be programmed through a user-friendly environment consisting of an assembler and a remote operation interface. Our approach aims to support a wide variety of student projects in our engineering curriculum, increase students productivity and decrease the development time. Through the proposed implementation, students are introduced to RISC architecture concepts, SOPC design and assembler structure. The reusability of the hardware permits flexible materialization of future projects to suit a variety of educational needs. The proposed inexpensive solution forms a complete educational environment suitable for undergraduate use.
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Keywords


System-On-A-Chip, System-On-A-Programmable-Chip, Field-Programmable-Gate-Array, Processor Core, Reduced-Instruction-Set-Computer

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