A Computer Architecture Educational System Based on a 32-bit RISC Processor
(*) Corresponding author
the author of the article can submit here a request for assignment of a DOI number to this resource!
Cost of the service: euros 10,00 (for a DOI)
This paper describes the implementation of a system-on-a-programmable-chip (SOPC) development board to support computer architecture laboratories at a low cost. A commercial field-programmable gate-array (FPGA) was employed to develop our reduced-instruction-set-computer (RISC) soft processor core that may be programmed through a user-friendly environment consisting of an assembler and a remote operation interface. Our approach aims to support a wide variety of student projects in our engineering curriculum, increase students productivity and decrease the development time. Through the proposed implementation, students are introduced to RISC architecture concepts, SOPC design and assembler structure. The reusability of the hardware permits flexible materialization of future projects to suit a variety of educational needs. The proposed inexpensive solution forms a complete educational environment suitable for undergraduate use.
Copyright © 2018 Praise Worthy Prize - All rights reserved.
- There are currently no refbacks.
Please send any question about this web site to firstname.lastname@example.org
Copyright © 2005-2023 Praise Worthy Prize