Optimized FPGA Mapping of a Bit-serial Square Root Operator with Minimum Output Delay

S. Simard; J. G. Mailloux; R. Beguenane

doi:10.15866/ireit.v5i4.14605

Optimized FPGA Mapping of a Bit-serial Square Root Operator with Minimum Output Delay

S. Simard⁽¹⁾, J. G. Mailloux⁽²⁾, R. Beguenane^(3*)

^(*) Corresponding author

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Abstract

We propose an FPGA implementation of a bit-serial square root operator based on an nonrestoring algorithm which optimally maps to the underlying hardware, and has minimal output delay. The most significant bit (MSB) of the square root is obtained right with the next clock cycle after input of the first bit of the radicand. Synthesis results for different radicand widths in the range of 8 to 64 bits targeting two different Xilinx families of FPGAs have shown this design to consume a number of 4-input LUTs at most twice the given width, and maximum clocking frequencies in excess of 100 MHz are possible in all cases. The proposed operator has been designed for use in advanced control loops, and has been found suitable for the intended purpose.
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Keywords

Bit Serial; Square root; Nonrestoring; FPGA; Delay

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