Control/Data Driven Embedded Systems High Level Modeling, Formal Verification and Simulation


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Abstract


The Unified Modeling Language (UML) is attracting more and more attention of Embedded Systems designers. On the other hand, rewriting logic is becoming interesting for distributed and concurrent systems formal specification and verification. On the other side, SystemC is becoming the standard system level language for Hw/Sw co-design. In this paper, we present our approach for Embedded Systems high level modeling, power consumption estimation, and formal verification following the Y-chart approach principles. The proposed approach starts by establishing the application and the architecture models using a subset of UML diagrams. In our case application is presented as a network of hierarchic data driven and control driven tasks that communicate via abstract channels. Two types of channels are identified: data channels and control channels. Data flow driven tasks behaviors are modeled through UML activity diagrams with coarse grained actions (CGAs) following Kahn Process Networks (KPN) model of computation semantics. Control driven tasks behaviors are modeled as finite state machines using UML statecharts. Hardware platform is modeled as UML structure diagram. Mapping is modeled through UML constraints. From UML models, a Maude specification is generated. We use this formal specification to formally validate system functionality against some undesirable properties and to estimate system power consumption at a high level of abstraction. The last step in our flow consists in SystemC code generation from UML models.
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Keywords


UML; Y-Chart Approach; KPN; Rewriting Logic; Maude; SystemC; Power Consumption Estimation; Simulation; Formal Verification

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References


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