On Cache Sizing in Multi-Core Cluster Architectures


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Abstract


With multi-core products hitting every market segment, we focus on a 16 core cluster-based architecture comprised of 4 clusters. Assuming the L1 cache memories are private, we conduct SPEC92 simulations to study the effect of the block  size, associativity, and cache size on the L1 cache hit rate. We observed significant drops in hit rate as the number of processors per cluster was increased from 1 to 4 with the largest drop occurring when boosting the number of processors from 1 to 2.  This result leads to discouraging the design of small clusters with less than 4 cores per cluster and confirms that 4-core clusters are properly sized. In caches of at least 16KB and with 1024 blocks, we observed no significant benefit to increasing the associativity beyond 8, and identified the best block sizes to be 256B and 128B.  Furthermore, hit rate improvements due to quadrupling the number of blocks and consequently the cache size were insignificant for block sizes of 64B or higher in caches with at least 256 blocks. For the SPEC92 benchmark, a 128KB 8-way set associative L1 cache with a  block  size of 64B  is adequate.
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Keywords


Multi-Core Architectures; 4-Way CMP Clusters; Cache Performance

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References


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