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The Design of an Ultra-Low-Power 7.5 GHz LNA in 0.13µm CMOS Technology with Cascode and Common-Source Topology


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DOI: https://doi.org/10.15866/iree.v15i4.18226

Abstract


An ultra-low-power, low-noise amplifier (LNA) at 7.5GHz in 0.13µm CMOS technology is proposed in this paper. New and precise calculation for input impedance is calculated and compared to other works. The main purpose of the design is to diminish the power consumption of the LNA by utilizing two different voltage supplies. All calculations and simulations are performed by Advanced Design System (ADS), MATLAB, and HSPICE with TSMC 0.13 µm CMOS process. Noise Figure (NF), the input matching (S11), gain (S21), the output matching (S22), IIP3, and power dissipation are 0.98, -25dB, 14.73dB, -19dB, -7, and 570µW respectively.
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Keywords


0.13µm CMOS; Two Voltage Biasing; Ultra-Low-Power; Low Noise Amplifier

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References


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