The Analysis of SCR-Based ESD Protection Circuit with P-Drift and N+ Floating Region
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DOI: https://doi.org/10.15866/iree.v10i4.5819
Abstract
In this paper, a novel SCR (Silicon Controlled Rectifier)-based ESD(Electrostatic Discharge) protection circuit for power clamp is proposed. The proposed protection circuit has high holding voltage due to floating n+ region which reduces current gain of parasitic bipolar transistor. This characteristic makes it ensure latch-up immunity. The electrical characteristics of the proposed ESD protection circuit have been simulated by using Synopsys TCAD simulation tool. According to the simulation results, the proposed protection circuit has high holding voltage of about 4.61V to 8.75V as design variation. Also, it is verified by using TLP (Transmission Line Pulse) system. As a result of measurement, it has holding voltage of 15.7V to 19.35V as design variation and high robustness above HBM 6kV, MM 600V.
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Huang, et al.., “ESD protection design for advanced CMOS,” in Proc.SPIE, 2001, pp. 123–131
R.G Wagner, J. Soden and C.F. Hawkins "Extend and Cost of EOS/ESD Damage in an IC Manufacturing Process", in Proc. of the 15th EOS/ESD Symp., pp.49-55, 1993
Dwyer VM, Fanklin Aj, Cambell DS,. “Thermal failure in semiconductor devices,” Solid State Electronics, pp.553-560, 1990
http://dx.doi.org/10.1016/0038-1101(90)90239-b
C. Russ, M. P. J. Mergens, J. Armer, P. Jozwiak, G.Kolluri, L. Avery, and K. Vergaegem, “GGSCR: GGNMOS triggered silicon controlled rectifiers for ESD protection in deep submicron CMOS processes,” in Proc. EOS/ESD Symp., 2001, pp.22-31.
J. A. Salcedo, J. J. Liou, and J. C. Bernier, “Novel and robust silicon controlled rectifier(SCR) based devices for on-chip ESD protection,” IEEE Electron device Lett., vol. 25, no. 9, pp. 658-660, September 2004.
http://dx.doi.org/10.1109/led.2004.834736
Vashchenko, V.A., Sinkevitch, V.F., “Physical Limitaions of Semiconductor Devices”, Springer, p.340, 2008
http://dx.doi.org/10.1007/978-0-387-74514-5
Kui-Dong Kim, Jo-woon Lee, Sang-Jo Park, Yoon-sik Lee, Yong-Seo Koo, “A Study on the Novel SCR NANO ESD Protection Device Design and fabrication” in Proc. of the IKEEE, Vol.9,No.2,pp. 161-169, 2005.
M.D Ker, et. al., “How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on,” Journal of Electro- statics, Vol. 47, pp. 215-248, 1999.
http://dx.doi.org/10.1016/s0304-3886(99)00037-6
Yong Seo Koo, et. al., “Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology,” Microelectronics Journal, Vol. 40, pp. 1007-1012, 2009.
http://dx.doi.org/10.1016/j.mejo.2009.01.001
Sheng-Lyang Jang, et. al., “Temperature-dependent dynamic triggering characteristics of SCR-type ESD protection devices,” Solid-State Electronics, Vol.45, pp. 2005-2009, 2001.
http://dx.doi.org/10.1016/s0038-1101(01)00243-x
W.Y Chen, et. al., “Measurement on Snapback Holding voltage of High-Voltage LDMOS for Latch-up Consideration,” device and system, APCCAS 2008, pp. 61-64, 2008.
http://dx.doi.org/10.1109/apccas.2008.4745960
E. Ground and M. Hernandez, “Obtaining TLP-like Information from an HBM simulator,” EOS/ESD Symp., pp. 2A.3-1-2A.3-7, 2007.
http://dx.doi.org/10.1109/eosesd.2007.4401737
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