A Novel BIST Circuit for Testing and Analysis Parametric Faults in PLL

Abstract

A novel built-in self-test (BIST) circuit of a phase-locked loop (PLL) in RF applications is presented in this paper. The proposed BIST circuit can detecting and analysis possible parametric faults in any block such as the phase frequency detector (PFD), charge pump (CP), loop filter (LF), voltage-controlled oscillator (VCO) and divide-by-N (DBN) of the PLL circuitry. The key advantage of this approach is that it insures that the PLL characteristics are not altered by adapting the BIST circuit. In order to reduce the chip area overheard, the proposed BIST circuit uses all existing blocks in PLL for measuring, analysis and testing parametric fault affected the circuit under test (CUT). The phase frequency detector circuit is used as a test stimulus generator and the oscillation frequency of VCO /divide-by-N circuit (DBN) as a measuring and analysis device. By building a test stimulus generator circuit and signature analyzer devices for the PLL, it can solve analog nodes loading problem and facilities the test accessibility. Fault simulation results indicate the characteristics of the proposed BIST circuit for detecting parametric faults, namely, excellent fault coverage (100%).
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