A DSP-Based Implementation of HEVC Encoder

Mohamed Maazouz; Noureddine Batel; Nejmeddine Bahri; Nouri Masmoudi

doi:10.15866/irecos.v11i10.10172

A DSP-Based Implementation of HEVC Encoder

Mohamed Maazouz^(1*), Noureddine Batel⁽²⁾, Nejmeddine Bahri⁽³⁾, Nouri Masmoudi⁽⁴⁾

^(*) Corresponding author

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DOI: https://doi.org/10.15866/irecos.v11i10.10172

Abstract

The new High Efficiency Video Coding (HEVC) standard will sooner replace the H.264/AVC standard and will be embedded in the majority of multimedia devices (smartphones, digital camera, UHD TV). It is expected to reduce the bit rate by half for the same quality compared to its predecessor H.264/AVC. However, the complexity and computational time for HEVC are much higher makinghard to achieve a real-time embedded solution for HEVC encoder with classic embedded processor technology. Consequently, new technologies of programmable processors such multicore Digital signal Processor (DSP) offer a very promising solution to overcome these constraints. In this paper, an optimized implementation of HEVC video encoder on a single core among the eight cores of TMS320C6678 DSP is presented in order to move afterwards to a multicore implementation. Based on the DSP architectural features, various Single-instruction-multiple-data (SIMD) optimizations are adopted to optimize the encoding time of the most consuming functions. Combined with the integrated fast encoding configuration in the reference HEVC software HM12.1, experimental results show that the whole proposed optimizations on a single core running at 1.25 GHz allow saving up to 78% of the encoding time with an acceptable distortion in terms of PSNR and bit-rate. The obtained results will make possible to achieve a real-time implementation when exploiting the multicore features.
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Keywords

Assembly Language; Digital Signal Processors; Distortion Functions; HEVC Encoder

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