A DSP-Based Implementation of HEVC Encoder
(*) Corresponding author
The new High Efficiency Video Coding (HEVC) standard will sooner replace the H.264/AVC standard and will be embedded in the majority of multimedia devices (smartphones, digital camera, UHD TV). It is expected to reduce the bit rate by half for the same quality compared to its predecessor H.264/AVC. However, the complexity and computational time for HEVC are much higher makinghard to achieve a real-time embedded solution for HEVC encoder with classic embedded processor technology. Consequently, new technologies of programmable processors such multicore Digital signal Processor (DSP) offer a very promising solution to overcome these constraints. In this paper, an optimized implementation of HEVC video encoder on a single core among the eight cores of TMS320C6678 DSP is presented in order to move afterwards to a multicore implementation. Based on the DSP architectural features, various Single-instruction-multiple-data (SIMD) optimizations are adopted to optimize the encoding time of the most consuming functions. Combined with the integrated fast encoding configuration in the reference HEVC software HM12.1, experimental results show that the whole proposed optimizations on a single core running at 1.25 GHz allow saving up to 78% of the encoding time with an acceptable distortion in terms of PSNR and bit-rate. The obtained results will make possible to achieve a real-time implementation when exploiting the multicore features.
Copyright © 2016 Praise Worthy Prize - All rights reserved.
K. R. Rao, D. N. Kim, and J. J. Hwang, High Efficiency Video Coding(HEVC). Springer Netherlands, 2014.
G. J. Sullivan, J.-R. Ohm, W.-J. Han, and T. Wiegand, “Overview of the High Efficiency Video Coding (HEVC) Standard,” Circuits Syst. Video Technol. IEEE Trans. On, vol. 22, no. 12, pp. 1649–1668, Dec. 2012.
C. Park, B.-G. Kim, G.-S. Hong, and S.-K. Kim, “Fast Coding Unit (CU) Depth Decision Algorithm for High Efficiency Video Coding (HEVC),” in Advances in Computer Science and its Applications, Springer Berlin Heidelberg, 2014, pp. 293–299.
F. Belghith, H. Kibeya, H. Loukil, M. A. B. Ayed, and N. Masmoudi, “A new fast motion estimation algorithm using fast mode decision for high-efficiency video coding standard,” J. Real-Time Image Process., pp. 1–17, Feb. 2014.
Y.-J. Ahn and D. Sim, “Square-type-first inter-CU tree search algorithm for acceleration of HEVC encoder,” J. Real-Time Image Process., pp. 1–14, Feb. 2015.
K. Chen, Y. Duan, L. Yan, J. Sun, and Z. Guo, “Efficient SIMD optimization of HEVC encoder over X86 processors,” presented at the Signal & Information Processing Association Annual Summit and Conference (APSIPA ASC), 2012 Asia-Pacific, 2012, pp. 1–4.
Y.-J. Ahn, T.-J. Hwang, D.-G. Sim, and W.-J. Han, “Implementation of fast HEVC encoder based on SIMD and data-level parallelism,” EURASIP J. Image Video Process., vol. 2014, no. 1, pp. 1–19, Mar. 2014.
P. Piñol, H. Migallón, O. López-Granado, and M. P. Malumbres, “Slice-based parallel approach for HEVC encoder,” J. Supercomput., vol. 71, no. 5, pp. 1882–1892, Dec. 2014.
P. Piñol, H. Migallón, O. López-Granado, and M. P. Malumbres, “Parallel strategies analysis over the HEVC encoder,” J. Supercomput., vol. 70, no. 2, pp. 671–683, Mar. 2014.
“IEEE Xplore Document - Hybrid Zero Block Detection for High Efficiency Video Coding.” [Online]. Available: http://ieeexplore.ieee.org/document/7373636/. [Accessed: 15-Sep-2016].
E. Kalali, A. C. Mert, and I. Hamzaoglu, “A computation and energy reduction technique for HEVC Discrete Cosine Transform,” IEEE Trans. Consum. Electron., vol. 62, no. 2, pp. 166–174, May 2016.
I. Zupancic, S. G. Blasi, E. Peixoto, and E. Izquierdo, “HEVC encoder optimisations using adaptive coding unit visiting order,” in 2016 IEEE International Conference on Image Processing (ICIP), 2016, pp. 794–798.
D. Jun, S.-C. Lim, J. Lee, H. Lee, J. Kim, J. Kang, J. Seok, Y. Kim, S. Jung, H.-Y. Kim, and J. S. Choi, “Development of an ultra-HD HEVC encoder using SIMD implementation and fast encoding schemes for smart surveillance system,” J. Supercomput., pp. 1–21, Jul. 2016.
F. Yao, X. Zhang, Z. Gao, and B. Yang, “Fast mode and depth decision algorithm for HEVC intra coding based on characteristics of coding bits,” in 2016 IEEE International Symposium on Broadband Multimedia Systems and Broadcasting (BMSB), 2016, pp. 1–4.
Q. Hu, Z. Shi, X. Zhang, and Z. Gao, “Fast HEVC intra mode decision based on logistic regression classification,” in 2016 IEEE International Symposium on Broadband Multimedia Systems and Broadcasting (BMSB), 2016, pp. 1–4.
“IEEE Xplore Document - Accelerating HEVC Motion Estimation Using GPU.” [Online]. Available: http://ieeexplore.ieee.org/document/7545033/. [Accessed: 15-Sep-2016].
G. Cebrián-Márquez, J. L. Martínez, and P. Cuenca, “A pre-analysis algorithm for fast motion estimation in HEVC,” in 2016 IEEE International Conference on Image Processing (ICIP), 2016, pp. 2013–2017.
S. Jia, W. Ding, Y. Shi, and B. Yin, “A fast sub-pixel motion estimation algorithm for HEVC,” in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, pp. 566–569.
F. Pescador, M. J. Garrido, E. Juarez, and C. Sanz, “On an implementation of HEVC video decoders with DSP technology,” in 2013 IEEE International Conference on Consumer Electronics (ICCE), 2013, pp. 121–122.
S. Kim, D.-K. Lee, C.-B. Sohn, and S.-J. Oh, “Fast motion estimation for HEVC with adaptive search range decision on CPU and GPU,” in 2014 IEEE China Summit International Conference on Signal and Information Processing (ChinaSIP), 2014, pp. 349–353.
G. Bjontegaard, “Calculation of average PSNR differences between RD-curves.” ITU-T,STUDY Question 6/16, Thirteenth Meeting: Austin, Texas, USA, 02-Apr-2001.
Ayadi, L., Neji, N., Loukil, H., Ben Ayed, M., Masmoudi, N., High-Performance Hardware Interpolation Architecture for High Efficiency Video Coding Decoder, (2016) International Review on Computers and Software (IRECOS), 11 (9), pp. 764-772.
Dhahri, S., Zitouni, A., Torki, K., An Adaptive Motion Estimator Design for High Performances H.264/AVC Codec, (2013) International Review of Automatic Control (IREACO), 6 (2), pp. 221-227.
Feki, O., Grandpierre, T., Masmoudi, N., Akil, M., Optimized Implementation of H.264/AVC Motion Estimation on a Mixed Architecture Using SynDEx-Mix, (2016) International Review on Computers and Software (IRECOS), 11 (5), pp. 395-402.
Essalmi, A., Mahmoudi, H., Bennassar, A., Abbou, A., Zahraoui, Y., Akherraz, M., Real Time Implementation of Sliding Mode Control for Induction Motor Drives Using dSPACE, (2015) International Review of Electrical Engineering (IREE), 10 (1), pp. 36-41.
Alaeddine, H., Baghious, E., Burel, G., Block Robust Algorithm for Network Echo Cancellation, (2013) International Journal on Communications Antenna and Propagation (IRECAP), 3 (1), pp. 68-77.
Jagadeesh, B., Kumar, P., Reddy, P., Fuzzy Inference System Based Robust Digital Image Watermarking in DWT-DCT Domain Using Human Visual System, (2016) International Review on Modelling and Simulations (IREMOS), 9 (4), pp. 265-270.
Velayudham, A., Kanthavel, R., Kumar, K., A Novel and Hybrid Optimization Mechanism For Denoising And Classification Of Medical Images using DTCWPT And Neuro-Fuzzy Classifiers, (2014) International Review on Computers and Software (IRECOS), 9 (3), pp. 513-525.
Sumathi, T., Karthikeyan, T., An Improved Identification System Using Iris Based on Curvelet Transform and WBCT, (2014) International Review on Computers and Software (IRECOS), 9 (8), pp. 1320-1327.
Gattim, N., Rajesh, V., Multimodal Medical Image Fusion Under Redundant Transforms, (2015) International Review on Computers and Software (IRECOS), 10 (3), pp. 241-248.
- There are currently no refbacks.
Please send any question about this web site to email@example.com
Copyright © 2005-2023 Praise Worthy Prize