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High-Performance Hardware Interpolation Architecture for High Efficiency Video Coding Decoder


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DOI: https://doi.org/10.15866/irecos.v11i9.9753

Abstract


The fractional sample interpolation process is one of the most computationally intensive parts of video decoder based on High Efficiency Video Coding (HEVC) standard. Therefore, in this paper, we propose high performance hardware interpolation architecture for inter-prediction which is useful for motion compensation (MC) module in the HEVC decoder. For this component, we propose a highly parallel architecture and a pipelined hardware implementation achieving 8×8 Prediction Unit (PU) interpolation in only 30 clock cycles. Experimental results show that our architecture can achieve up to 3.2 pixels/cycle at 125 MHz on field-programmable gate array technology (FPGA) and the corresponding performance can support the processing of Quad Full High Definition (QFHD, 3840×2160)@30 fps. The gate count of the resulting Application-Specific Integrated Circuit (ASIC) implementation in 65 nm technology is 36.7 k.
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Keywords


High Efficiency Video Coding; Hardware Implementation; Interpolation; Motion Compensation

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References


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