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Reusable Data-Path Architecture for Encryption-then-Authentication on FPGA

Yasir Amer Abbas(1*), Razali Jidin(2), Norziana Jamil(3), Muhammad Reza Z'aba(4)

(1) Department of electronics & communication engineering, Universiti Tenaga Nasional, Malaysia
(2) Department of electronics & communication engineering, Universiti Tenaga Nasional, Malaysia
(3) Department of electronics & communication engineering, Universiti Tenaga Nasional, Malaysia
(4) MIMOS Berhad, Technology Park Malaysia, Malaysia
(*) Corresponding author


DOI: https://doi.org/10.15866/irecos.v11i1.8367

Abstract


This paper proposes reusable data-path architecture for lightweight cryptography algorithms, reusing some similar hardware components for both encryption and authentication. In addition to efforts by many researches to optimize hardware architectures, to reduce hardware resources, our proposal is to reuse identical functional blocks within crypto-algorithms targeting for more secure cryptography like Message Authentication Code (MAC), authenticated encryption such as Encrypt-then-MAC (EtM) on Field Programmable Gate Arrays (FPGA). For this proposed reusable data-path, we have chosen LED algorithm for encryption and then PHOTON to generate the MAC code. Instead of creating two different circuits, one for PHOTON and another for LED, our proposal’s is to reuse some of identical block functions repeatedly, therefore reduce the size of required circuit area. Reuse of resources or identical functions however require controllers that enable sharing of data path that can also has different “rounds” of transforms required for different modes either PHOTON or LED in this case, in addition to controllers for individual algorithm. Also to enable comparable computation speed, the data-path has to be further refined, an improvement needed at least on par or better than the current techniques.  For PHOTON data-path, we have improved performance of Mix-Columns, focusing on lengthy clock cycle of Galois polynomial multiplication. The results show that this proposed EtM hardware architecture achieves significant improvements, up to 587 MHz, 1336 Mbps and 3.2 Mbps/slices, for maximum frequency, throughput and efficiency, respectively.
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Keywords


Lightweight Cryptography; Reusable Data Path Architecture; ETM; FPGA

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References


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