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A CPU-Guided Dynamic Voltage and Frequency Scaling (DVFS) of Off-Chip Buses in Homogenous Multicore Processors

Mutaz Al-Tarawneh(1*), Ziyad Ahmed Al Tarawneh(2), Saif E. A. Alnawayseh(3)

(1) Computer Engineering Department, Faculty of Engineering, Mu’tah Univesity, Jordan
(2) Electrical Engineering Department, Faculty of Engineering, Mu’tah Univesity, Jordan
(3) Electrical Engineering Department, Faculty of Engineering, Mu’tah Univesity, Jordan
(*) Corresponding author


DOI: https://doi.org/10.15866/irecos.v10i7.6742

Abstract


This paper proposes a dynamic voltage and frequency scaling (DVFS) technique for off-chip buses in multicore processors with identical processing cores. The proposed technique captures application’s sensitivity to off-chip access latency and dynamically tunes power parameters of the off-chip bus accordingly. Full system simulation has been used to evaluate the proposed idea in two main types of multicore architectures; Type 1 consists of complex superscalar processor cores while Type 2 consists of simple scalar processors. Simulation results have shown that the proposed DVFS scheme has achieved better results in Type 1; it reduces total off-chip bus energy, improves off-chip bandwidth energy efficiency and has negligible effect on processor performance.
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Keywords


DVFS; Multicore; Off-chip Bus; Power; Performance

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References


M. Själander, M. Martonosi, and S. Kaxiras, Power-Efficient Computer Architectures: Recent Advances, Synthesis Lectures on Computer Architecture, December 2014, Vol. 9, No. 3 , Pages 1-96.
http://dx.doi.org/10.2200/s00611ed1v01y201411cac030

S. Borkar and A. A. Chien, The future of microprocessors, Communications of the ACM, May 2011,vol. 54, no. 5, pp. 67–77.
http://dx.doi.org/10.1145/1941487.1941507

Lee, J., Nam ,B., Yoo, H., Dynamic Voltage and Frequency Scaling (DVFS) scheme for multi-domains power management, Proceedings Of the IEEE Asian Solid-State Circuits Conference, 2007, pp. 360-363.
http://dx.doi.org/10.1109/asscc.2007.4425705

Radhamani, A.S., Baburaj, E., High performance power efficient scheduler for multicore processor in real time applications, (2014) International Review on Computers and Software (IRECOS), 9 (2), pp. 337-346.

Rajan, D.,Zuck, R., Poellabauer, C., Workload-Aware Dual-Speed Dynamic Voltage Scaling, Proceedings Of the 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2006, pp. 251-256.
http://dx.doi.org/10.1109/rtcsa.2006.64

A. Chandrakasan, S. Sheng and R. Brodersen, Low-power CMOS digital design, IEEE Journal of Solid-State Circuits, Vol. 27, no. 4,1992, pp. 473-484.
http://dx.doi.org/10.1109/4.126534

Sueur,E. L., Heiser, G., Dynamic voltage and frequency scaling: the laws of diminishing returns, Proceedings Of the International Conference on Power aware Computing and Systems, 2010, pp. 1-8.

Brock, B., Rajamani, K., Dynamic power management for embedded systems [SOC design], Proceedings Of the IEEE International SOC Conference, 2003, pp. 416-419.
http://dx.doi.org/10.1109/soc.2003.1241556

Pedram, M., Power optimization and management in embedded systems, Proceedings of the Asia and South Pacific Design Automation Conference, 2001, pp. 239-244.
http://dx.doi.org/10.1109/aspdac.2001.913312

Singleton, L., Poellabauer, C., Schwan, K., Monitoring of Cache Miss Rates for Accurate Dynamic Voltage and Frequency Scaling, Proceedings of the 12th Annual Multimedia Computing and Networking Conference, 2005.
http://dx.doi.org/10.1117/12.590806

Choi, K., Soma, R., Pedram, M., Dynamic Volatage and Frequency Scaling Based on Workload Decomposition, Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004,pp. 174-179.
http://dx.doi.org/10.1145/1013235.1013282

K. Choi, R. Soma and M. Pedram, Fine-grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-off Based on the Ratio of Off-chip Accesses to On-chip Computation Times, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 1, Jan. 2005,pp. 4-9.
http://dx.doi.org/10.1109/tcad.2004.839485

S. Djosic and M. Jevtic, Dynamic voltage and frequency scaling algorithm for fault-tolerant real-time systems, Microelectronics Reliability, Vol. 53, Issue 7, 2013, pp. 1036-1042.
http://dx.doi.org/10.1016/j.microrel.2013.03.012

A. Ahmadian, M. Hosseingholi and A. Ejlali, Discrete feedback-based dynamic voltage scaling for safety critical real-time systems, ScientiaIranica, Vol. 20, Issue 3, 2013, pp. 647-656.
http://dx.doi.org/10.1016/j.scient.2012.11.009

AbouGhazaleh, N., Ferreira, A., Rusu, C., Xu, R., Liberato, F., Childers, B., Mosse, D., Melhem, R., Integrated CPU and l2 cache voltage scaling using machine learning, Proceedings Of the ACM SIGPLAN/ SIGBED Conference on Languages, Compliers and Tools for Embedded Systems, 2007, pp. 41-50.
http://dx.doi.org/10.1145/1254766.1254773

Chen, X., Xu, Z., Kim, H., Gratz, P. V., Dynamic Voltage and Frequency Scaling for Shared Resources in Multicore Processor Designs, Proceedings of the 50th ACM/EDAC/IEEE Design Automation Conference,2013, pp. 1-7.
http://dx.doi.org/10.1145/2463209.2488874

V. Hanumaiah and S. Vrudhula, Energy-Efficient Operation of Multicore Processors by DVFS, Task Migration , and Active Cooling, IEEE Transaction on Computers, Vol. 63, Issue 2, 2014, pp. 349-360.
http://dx.doi.org/10.1109/tc.2012.213

Mishra, A. K., Srikantaiah, S., Kandemir, M., Das, C. R., CPM in CMPs: Coordinated Power Management in Chip Multiprocessors, Proceedings of the International Conference for High Performance Computing, Networking and Analysis (SC), 2010, pp. 1-12.
http://dx.doi.org/10.1109/sc.2010.15

Puttaswamy, K., Choi, K., Park, J. C., Mooney III, V. J., Chatterjee, A., Ellervee, P., System Level Power-performance Trade-offs in Embedded Systems Using Voltage and Frequency Scaling of Off-chip buses and Memory ,Proceedings of the 15th International Symposium on Systems Synthesis, 2002, pp. 225-230.
http://dx.doi.org/10.1109/isss.2002.1227182

F. Catthoor, S. Wuytack, E. De Greef. F. Balasa, L. Nachtergaele and A. Vandecappelle, Exploration of Memory Organization for Embedded Multimedia System Design( Kluwer academic publishers, 1998).
http://dx.doi.org/10.1007/978-1-4757-2849-1_9

Suresh, D. C., Agrawal, B., Najjar, W., Yang, J., A Tunable Bus Encoder for Off-chip Data Buses, Proceedings of the International Symposium on Low Power Electronics and Design, 2005, pp. 319-322.
http://dx.doi.org/10.1109/lpe.2005.195539

J.Renau, B. Fraguela, J. Tuck, W. Liu, M.Prvulovic, L.Ceze and P. Montesinos, SESC simulator, 2005.

Woo,S. C., Ohara, M., Torrie, E., Singh, J. P., Gupta, A., The SPLASH-2 Programs: Characterization and Methodological Considerations, Proceedings of the 22ndAnnual International Symposium on Computer Architecture, 1995, pp. 24-36.
http://dx.doi.org/10.1109/isca.1995.524546


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