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Delay and Performance Estimation for a 4-bit Even Parity Bit Generator Using the Logical Effort Model
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DOI: https://doi.org/10.15866/irecos.v10i8.6279
Abstract
Recent digital applications require high speed and high performance designs. The circuit design can be implemented using different types of logic gates. The logic gates are classified into two types; primitive and compound (complex) gates. Any complex logic circuit diagram can be converted into primitive using one type of universal gates; such as the NAND gates or the NOR gates only. The combinational circuits and any functional block can also be implemented using the NAND or the NOR gates only. This article shows how to build a 4-bit even parity bit generator using both universal gate types: the implementation using NAND gates only and the implementation for the 4-bit even parity bit generator using NOR gates only. A performance comparison between these two implementations, with different output loads in each case, is achieved to study the impact of the output load on the circuit delay. It will also determine which type of universal gates can be used to get better performance (delay) readings by using the logical effort technique. The logical effort is a technique used to estimate the static logic circuit delay and the power dissipated by a circuit. It helps designers make their right decisions about the delay and the power for a given design before the real implementation begins.
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