A CMOS-Based Dual Logic Mode Gate for Analysis of Logical Effort in Sequential and Combinational Circuit
Newly, a novel Dual Mode Logic (DML) family is utilized in the proposed technology. This logic performs operation in two modes, namely static and dynamic modes. DML gates can be swapped between the modes on-the-fly, which has very low power dissipation inthe static mode and high performance in the dynamic mode. A typical DML gate is very simple and has static logic family gate and an extra clocked transistor. The logical effort (LE) method is applied in the CMOS-based DML family. This method allows path length reduction, delay optimization and estimation of DML logic. In the existing system, the output attained from the multiplier and D-flip flop has less accuracy and high delay. In the proposed work, DML is designed based on CMOS to improve the accuracy. DML is established in multiplier and D-flip flop, which efficiently decreases the delay and energy dissipation. The LE is computed for both DML based multiplier and DML D-flip flops of the registers. The proposed framework provides better accuracy and has less delay and power dissipation when compared to the multiplier and D-flip flop without DML logic.
Copyright © 2015 Praise Worthy Prize - All rights reserved.
P. Lakshmisree and M. Raghu, "Design of Sub Threshold DML Logic Gates with Power Gating Techniques," International Journal of Research in Engineering and Technology (IJRET), vol. 3, pp. 174-180, 2014.
S. Venugopal, S. Jacob, and P. S. Kammath, "Design of up/down counter based on dual mode logic and Low power Hybrid dual mode dynamic flip-flop," American Journal of Engineering Research (AJER), vol. 3, pp. 1-6, 2014.
M. S. A. Nasreen and D. T. Kavitha, "Design of Carry Look Ahead Adder using Subthreshold Dual Mode Logic," International Journal on Applied Information and Communication Technology (IJAICT), vol. 1, pp. 307-312, 2014.
A. F. Itamar Levi, "Dual Mode LogicDesign for Energy Efficiency and High Performance," IEEE Access, vol. 1, pp. 258-265, 2013.
B. Mesgarzadeh, "Logical Effort of CMOS 4-2 Compressors for Arithmetic Circuits."
S. Vaidya and D. Dandekar, "Delay-power performance comparison of multipliers in vlsi circuit design," International Journal of Computer Networks & Communications (IJCNC), vol. 2, pp. 47-56, 2010.
C. Marimuthu, P. Thangaraj, and A. Ramesan, "Low power shift and add multiplier design," arXiv preprint arXiv:1006.1179, vol. 2, pp. 12-22, 2010.
S. S. Akansha Rajput, "Implementation of CMOS circuits In Logic optimization using logical effort technique " International Journal Of Engineering And Computer Science, vol. 2, pp. 3106-3110 2013.
M. r. Rani, "Logic Effort of CMOS based Dual Mode Logic Gates," International Journal of Advanced Research in Computer Engineering & Technology (IJARCET), vol. 3, pp. 3703-3710, 2014.
D. Baran, M. Aktan, and V. G. Oklobdzija, "Energy efficient implementation of parallel CMOS multipliers with improved compressors," in ACM/IEEE international symposium on Low power electronics and design, 2010, pp. 147-152.
J. N. Reddy, T. Sathyanarayana, and M. K. Baba, "Subthreshold Dual Mode Logic," Bulletin of Electrical Engineering and Informatics, vol. 3, pp. 141-148, 2014.
J. G. Bo Marr, Brian Degnan, David V. Anderson, Paul Hasler, "Error Immune Logic for Low-Power Probabilistic Computing " VLSI design, pp. 1-9, 2010.
I. Levi, O. Bass, A. Kaizerman, A. Belenky, and A. Fish, "High speed dual mode logic carry look ahead adder," in 2012 IEEE International Symposium on Circuits and Systems (ISCAS),, 2012, pp. 3037-3040.
A. Kaizerman, S. Fisher, and A. Fish, "Subthreshold dual mode logic," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, pp. 979-983, 2013.
A. Kabbani, "Logical effort based dynamic power estimation and optimization of static CMOS circuits," Integration, the VLSI journal, vol. 43, pp. 279-288, 2010.
M. Avital and A. Fish, "Secured Dual Mode Logic (DML) as a countermeasure against Differential Power Analysis," in IEEE International Symposium on Circuits and Systems (ISCAS) 2014, pp. 810-813.
I. Levi, A. Kaizerman, and A. Fish, "Low voltage dual mode logic: Model analysis and parameter extraction," Microelectronics Journal, vol. 44, pp. 553-560, 2013.
I. Levi, A. Belenky, and A. Fish, "Logical Effort for CMOS-Based Dual Mode Logic Gates," IEEE Transactions On Very Large Scale Integration (Vlsi) Systems, vol. 22, 2014.
Saravanakumar, N., Nirmal Kumar, A., Vijeyakumar, K.N., Ananda Moorthy, M.K., Design of high speed serial-serial multiplier for OFDM applications, (2013) International Review on Computers and Software (IRECOS), 8 (10), pp. 2495-2499.
Rosi, A., Seshasayanan, R., Nisha, A., Design of high speed modulo multipliers, (2014) International Review on Computers and Software (IRECOS), 9 (7), pp. 1263-1270.
Wang, X., Dinh, A., Teng, D., Ultra wide-band CMOS digital transmitter IC for low-power biomedical radar sensing and sensor network: Design and evaluation, (2011) International Journal on Communications Antenna and Propagation (IRECAP), 1 (1), pp. 46-54.
Attaran, A., Nikan, S., Razzaghpour, M., CMOS class AB power amplifier linearization by feed forward technique for wireless communications, (2011) International Journal on Communications Antenna and Propagation (IRECAP), 1 (1), pp. 29-33.
- There are currently no refbacks.
Please send any question about this web site to email@example.com
Copyright © 2005-2022 Praise Worthy Prize