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A CMOS-Based Dual Logic Mode Gate for Analysis of Logical Effort in Sequential and Combinational Circuit

Shri Saraswathy(1*), F. V. Jayasudha(2)

(1) Department of ECE, Sathyabama University, India
(2) Department of ECE, Sathyabama University, India
(*) Corresponding author


DOI: https://doi.org/10.15866/irecos.v10i1.5260

Abstract


Newly, a novel Dual Mode Logic (DML) family is utilized in the proposed technology. This logic performs operation in two modes, namely static and dynamic modes. DML gates can be swapped between the modes on-the-fly, which has very low power dissipation inthe static mode and high performance in the dynamic mode. A typical DML gate is very simple and has static logic family gate and an extra clocked transistor. The logical effort (LE) method is applied in the CMOS-based DML family. This method allows path length reduction, delay optimization and estimation of DML logic. In the existing system, the output attained from the multiplier and D-flip flop has less accuracy and high delay. In the proposed work, DML is designed based on CMOS to improve the accuracy. DML is established in multiplier and D-flip flop, which efficiently decreases the delay and energy dissipation. The LE is computed for both DML based multiplier and DML D-flip flops of the registers. The proposed framework provides better accuracy and has less delay and power dissipation when compared to the multiplier and D-flip flop without DML logic.
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Keywords


Complementary Metal Oxide Semiconductor (CMOS); Dual Mode Logic (DML); Logical Effort (LE)

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