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Acceleration of Inter-Task Routing for JIT Compilation Reconfigurable Computing Platform Using Customized Processor

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In Online Task Placement of Reconfigurable Computing platforms, the tasks are precompiled as rectangles with fixed height and width. Thus, there remains some empty areas between the tasks that can’t be filled with any of those fixed shape tasks. If compilation of the tasks to fill the non-occupied areas is done at runtime and inside the platform, the typical tasks can be fabricated in the best shape and placed on such areas of the FPGA to reduce the rejection rate metric. This is called Just-In-Time FPGA Compilation. Executing compilation algorithms on embedded processor of the platform is a time-consuming work and is not normally feasible for real user applications. In this paper, a customized processor has been proposed as a promising solution to speed up the execution time of compilation algorithms used in JIT reconfigurable computing platform. The proposed processor is customized for the routing which is time-consuming phase. SimpleScalar simulator toolset is used to provide high flexible performance processor architecture. Customized co-processor and memory has been added to the processor. Regarding this specification, we achieved 10.13X speedup compared with the embedded general purpose processor.
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Reconfigurable Computing Platform; Routing Acceleration; Customized Processor

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