Design of High Speed Modulo Multipliers

A. Rosi(1*), R. Seshasayanan(2), A. Nisha(3)

(1) Anna university, India
(2) Anna university, India
(3) Anna university, India
(*) Corresponding author

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In this paper we present the performance of proposed modulo2n -1 and 2n +1 multiplier that adopts the pipeline technique. Modulo multipliers are often adopted to implement long and repetitive multiplications of cryptographic and signal processing algorithms. In this paper the proposed pipelined modulo multiplier architecture uses radix-8 booth algorithm. The numbers of partial product are reduced drastically when compared with radix-4 booth algorithm. Pipelining technique is applied in our proposed architecture to reduce the delay and analyzed for various bit width of 2n-1 and 2n+1 modulo multiplier.
The proposed pipelined modulo multiplier is being analyzed on FPGA environment. The proposed architecture is synthesized using Xilinx 12.2. By comparing with existing modulo multiplier our proposed pipelined modulo multiplier (2n -1 , 2n +1 ) shows improvement in speed of about 30% to 50% for n=16 ,32and 64 bits respectively. In the proposed modulo multiplier pipeline technique is exploited in smarter way where we never allowed the area to get increased above 15% compare to existing modulo multiplier. Thus with a insignificant increase in area we can able to achieve a speed of about 30 t0 50%.

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Residue Number System (RNS); Radix-8 Booth; FPGA; Hard Multiple Generator; Modulo Multiplication

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R.Zimmermann, Efficient VLSI implementation of modulo (2n±1) addition and multiplication, in Proc. 14th IEEE Symp. Computer Arithmetic, Adelaide, Australia, Apr. 1999, pp. 158-167

C. Efstathiou, H.T. Vergos, and D. Nikolos, Modified Booth modulo 2n-1 mutlipliers IEEE Trans. Comput., vol. 53, no. 3, pp. 370-374, Mar. 2004.

C. Efstathiou, H.T. Vergos, G. Dimitrakopoulos, and D. Nikolos, Efficient diminished-1 modulo 2n+1 multipliers, IEEE Trans. Comput., vol. 54, no. 4, pp. 491-496, Apr. 2005.

Y.Ma, A simplified architecture for modulo (2n+1) multiplication, IEEE Trans. Comput., vol. 47, no. 3, pp. 333-337, Mar. 1998.

L.Sousa and R.chaves, A universal architecture for designing efficient modulo2n+1 multipliers, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 6, pp. 1166-1178, Jun. 2005.

J.W. Chen and R.H. Yao, Efficient modulo 2n+1 multipliers for diminished-1 representation, IET Circuits, Devices Syst., vol.4, no. 4, pp. 291-300, Jul. 2010.

G.W. Bewick, Fast Multiplication: Algorithms and Implementation, Ph.D. dissertation, Stanford Univ, Stanford, CA, 1994.

B.S. Cherkauer and E.G. Friedman, A hybrid radix-4/radix-8 low power signed multiplier architecture, IEEE Trans. Circuits Syst. II, Analog. Digit. Signal Process., vol. 44, n0. 8, pp. 656-659, Aug. 1997.

M.J. Flynn and S.F. Oberman, Advanced Computer Arithmetic Design New York: Wiley, 2001.

R. Muralidharan and C.H. Chang, Radix-8 Booth encoded modulo 2n-1 multipliers with adaptive delay for high dynamic range residue number system, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 5, pp. 982-993, Jun. 2011.

Ramya Muralidharan, and Chip-Hong Chang, Area-Power Efficient Modulo 2n-1 and Modulo 2n+1 Multipliers for {2n-1 ,2n ,2n+1} Based RNS, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 10, Oct. 2012.


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