Enhanced FPGA Implementation of the SHA-512 Hash Function

Fatma Kahri; Hassen Mestiri; B. Bouallegue; M. Machhout

doi:10.15866/irecos.v9i11.2071

Enhanced FPGA Implementation of the SHA-512 Hash Function

Fatma Kahri^(1*), Hassen Mestiri⁽²⁾, B. Bouallegue⁽³⁾, M. Machhout⁽⁴⁾

^(*) Corresponding author

Authors' affiliations

DOI: https://doi.org/10.15866/irecos.v9i11.2071

Abstract

In modern cryptographic hash function plays an important role. Hash function algorithms are widely used to provide authentication, security and services of integrity. The main computation block in SHA-512 algorithm is governed by a loop with high data dependence for which one implementation strategy is explored in this work as well as design efficiently mapped to hardware architecture. We propose an improved implementation of the SHA-512 hash family, with minimal operator latency, reduced hardware requirements, high frequency, and high throughput. The proposed design were implemented and validated in the FPGA Virtex. The FPGAs targets are XC5VLX30-3ff324, XC6VLX75T-3ff784.
Copyright © 2014 Praise Worthy Prize - All rights reserved.

Keywords

SHA-512; FPGA; Cryptography; Hardware

Full Text:

PDF

References

Alfred J. Menezes, Paul C. van Oorschot, Scott A. Vanstone, Handbook of Applied Cryptography, CRC Press, 1997.
http://dx.doi.org/10.1201/9781439821916

Benhadjyoussef, N., Elhadjyoussef, W., Machhout, M., Torki, K., Tourki, R., A cryptographic processor for 32 bit embedded system with resource-constraints, (2013) International Review on Computers and Software (IRECOS), 8 (1), pp. 132-143.

Mestiri, H., Benhadjyoussef, N., Machhout, M., Tourki, R., High performance and reliable fault detection scheme for the advanced encryption standard, (2013) International Review on Computers and Software (IRECOS), 8 (3), pp. 730-746.

M. Zeghid , B. Bouallegue, M.Machhout, A. baganne and R. Tourki “Architectural design features of a programmable high throughput reconfigurable SHA-2 Processor” , Journal of Information Assurance and Security, 2 (2008) 147-158.

R. Chaves, G. Kuzmanov, L. Sousa, S. Vassiliadis, Improving SHA-2 hardware implementations, in: CHES, 2006, pp. 298–310.
http://dx.doi.org/10.1007/11894063_24

H.E. Michail, G.S. Athanasiou, A.A. Gregoriades, C.L. Panagiotou, C.E. Goutis,High throughput hardware/software co-design approach for SHA-256 hashing cryptographic module in IPSec/IPv6, Global Journal of Computer Science and Technology 10 (4) (2010) 54–59..

D. Fedoryka, Fast Implementation of the Secure Hash Algorithm SHA-256 in Field Programmable Gate Arrays, George Mason University, 2004.

J;Philippe Aumasson, L Henzen W. Meier, SHA-3 proposal BLAKE varsion 1.3, decembre 16, 2010.

Robert P. McEvoy, Francis M. Crowe, Colin C. Murphy and William P. Marnane. Optimisation of the SHA-2 Family of Hash Functions on FPGAs.
http://dx.doi.org/10.1109/isvlsi.2006.70

National Institute of Standards and Technology, “Secure Hash Standard”, Federal Information Processing Standards 180-2, August 2002.

Kahri, F. ; Bouallegue, B. ; Machhout, M. ; Tourki, R. Sciences and Techniques of Automatic Control and Computer Engineering (STA), 2013 14th International Conference on Digital Objecten 2013 , Page(s): 152 – 157.
http://dx.doi.org/10.1109/sta.2013.6783122

F. Crowe, A. Daly, and W. Marnane. Single-chip FPGA im-plementation of a cryptographic co-processor. InProceed-ings of the International Conference on Field Programmable Technology, FPT 2004, pages 279–285, December 2004.
http://dx.doi.org/10.1109/fpt.2004.1393279

R. Lien, T. Grembowski, and K. Gaj. A 1 Gbit/s partially un-rolled architecture of hash functions SHA-1 and SHA-512. In CT-RSA 2004, volume 2964 of LNCS, pages 324–338. Springer, 2004.
http://dx.doi.org/10.1007/978-3-540-24660-2_25

M. McLoone and J. McCanny. Efficient single-chip imple-mentation of SHA-384 and SHA-512. InProceedings of the International Conference on Field Programmable Technol-ogy, FPT 2002, pages 311–314, December 2002.
http://dx.doi.org/10.1109/fpt.2002.1188699

N. Sklavos and O. Koufopavlou. Implementation of the SHA-2 Hash Family Standard Using FPGAs. The Journal of Supercomputing, 31:227–248, 2005.
http://dx.doi.org/10.1007/s11227-005-0086-5

K. K. Ting, S. C. L. Yuen, K.-H. Lee, and P. H. W. Leong. An FPGA based SHA-256 processor. InFPL, volume 2438 of LNCS, pages 577–585. Springer, 2002.

Ryan G, Laurent I , Graham J, Arnaud T , Nicolas V. Multi-mode operator for SHA-2 hash functions. Journal of Systems Architecture 53 (2007) 127–138
http://dx.doi.org/10.1016/j.sysarc.2006.09.006

Ricardo C, Georgi K ,Leonel S , Stamatis V. Improving SHA-2 Hardware Implementations. In proceeding of Cryptographic Hardware and Embedded Systems - CHES 2006, 8th International Workshop, Yokohama, Japan, October 10-13, 2006,
http://dx.doi.org/10.1007/11894063_24

Alaeddine, H.H., Alaeddine, A.H., Bazzi, O., Mohanna, Y., Wave-radio interferometer, (2012) International Journal on Communications Antenna and Propagation (IRECAP), 2 (1), pp. 16-22.

Divya Navamani, J., Lavanya, A., Vijayakumar, K., Implementation of voltage controlled multi device interleaved boost converter using FPGA, (2014) International Review on Modelling and Simulations (IREMOS), 7 (3), pp. 422-427.

Refbacks

There are currently no refbacks.

Username
Password
Remember me