High Performance Power Efficient Scheduler for MultiCore Processor in Real Time Applications


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Abstract


Heterogeneous multi-core architecture is becoming more and more appreciated as an option to exploit TLP and ILP simultaneously which reduces processor power consumption significantly and keeps the complexity of processor under control. Heterogeneous multicore processors with varying core frequency and voltage have been proposed as an alternative design to improve power efficiency over traditional homogeneous multicore system real time applications. We make the work for the effective thread fair scheduling based on cache in heterogeneous cores aiming at improving combined power efficiency and performance. Our thread based algorithm with wait free data structure has been implemented to identify the performance of the cores in terms of completion time. Then with the help of Dual Phase Scheduling algorithm power consumption is achieved in real time systems with heterogeneous core, and provide better power savings than the previous power aware scheduling techniques. Finally we formulated optimal Dynamic Voltage Frequency Scaling (DVFS) power aware scheduling to improve the power consumption in real time applications
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Keywords


Multi-Core; Wait Free Data Structure; Cloud Computing; Power Aware Scheduling; Real Time Application

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