Design of Vedic Architecture for High Speed DCT

Abstract

Discrete Cosine Transform (DCT) is a frequency transform which is extensively used as a transform codec for still, moving image and video compression. The performance of DCT architecture mainly depends on multiplier and adder. In conventional architecture, array multiplier and Ripple Carry Adder (RCA) gives enormous delay when the number of input bits become more. After having detailed literature review, it is decided to design high speed VLSI DCT architecture with Vedic Multiplier and Carry Select Adder (CSA) for better performance. The Vedic multiplier is based on Urdhva Tiryakbhyam, the most efficient Sutra or algorithm which reduces the delay for all types of computation. The functionality of the proposed architecture is simulated using Modelsim and synthesis of verilog HDL code is done using Xilinx ISE. Both the DCT architectures are compared and the result shows that the delay of Vedic multiplier becomes low. The synthesis results show that the combinational delay for Vedic multiplier is reduced by 36% than conventional array multiplier. The combinational delay for CSA is reduced by 35% than RCA. The proposed architecture would give better performance in terms of speed for image and other signal processing applications
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