Test Data Compression Using Multiple Run Length Code Technique

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System on chip is challenging, for both design and testing engineers due to its increase in power consumption. In test mode, the volume of the test data is extremely high when compared to normal mode, the switching activity which takes place between the test data thereby increases power consumption. The proposed technique includes hamming distance reordering of original test data, Column wise bit filling, difference vector technique and multiple run length code technique. It improves the compression ratio and reduces the average power and peak power of MINTEST test sets of ISCAS’89 benchmark circuits
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CBF; Don’t Care Bit Filling Technique; Hamming Distance Reordering; Multiple Run Length Code Technique

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