Design of High Speed Serial-Serial Multiplier for OFDM Applications
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Delays associated with high density multipliers are typically large and it is the main drawback of high frequency data manipulation. Optimizing the speed and area of the multiplier is a major design issue. A High Speed Serial-Serial Multiplier (HS-SSM) using half grid cycle for Ortho Frequency Division Multiplexing (OFDM) is proposed. In half grid cycling the data is fed at the input both during positive and negative edge of the clock. So more than one partial product is computed in each cycle. The computation of more than one partial product in each cycle reduces total delay of multiplication. The proposed HS-SSM and state-of the art multipliers are designed using VHDL coding and simulated using ALTERA QUARTUS II. The experimental results revealed that the proposed HS-SS multiplier performed better in terms of delay reduction. This accounts for the best Power Delay Product (PDP) and Area Delay Product (ADP) of the proposed multiplier. A HS-SS multiplier using half grid technique is proposed. Extensive comparison with the conventional and state-of-the art designs revealed the best performance of the proposed serial multiplier in terms of delay and PDP reduction. An implementation of the proposed multiplier design in OFDM block for signal processing revealed its suitability for high speed application.
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