High Performance FPGA Architecture for Dual Mode Processor of Integer Haar Lifting-Based Wavelet Transform

Haider Ismael Shahadi(1*), Razali Jidin(2), Wong Hung Way(3)

(1) Centre for Automation & Embedded Computing System, Tenaga National University (UNITEN), Putrajaya, Malaysia
(2) Centre for Automation & Embedded Computing System, Tenaga National University (UNITEN), Putrajaya, Malaysia
(3) Centre for Automation & Embedded Computing System, Tenaga National University (UNITEN), Putrajaya, Malaysia
(*) Corresponding author


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Abstract


Discrete Wavelet Transform (DWT) becomes a major part for many applications. Fast, low area, and low power consumption hardware for DWT is necessary for some new technologies such as OFDM transceiver and wireless multimedia sensor networks.  This paper presents efficient dual mode (decomposition and reconstruction) Integer Haar Lifting Wavelet Transform (IHLWT) architecture. The proposed architecture reduces the hardware requirements by exploiting the arithmetic operations redundancy which is involved in IHLWT computations. It is multiplier-free and it performs IHLWT with only a single adder and subtractor which have reconfigurable input buses to perform decomposition and reconstruction transformations. IEEE standard VHDL has been used to develop the proposed processor. This makes the design vendor independent and therefore easily portable across FPGA devices from multiple vendors. The generic design is flexible and can perform any arbitrary signal length. The synthesis of the processor showed that it requires low number of CLB-slices and low power consumption with high operating-frequency for various Xilinx FPGA devices. The processor has been successfully implemented and tested on Xilinx Spartan6-SP601 Evaluation Board. The implemented hardware has been tested in real time by using many recording audio signals. All the implemented hardware results were identical 100% with IHLWT software results.
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Keywords


Lifting Wavelet Transform (LWT); Field Programmable Gate Array (FPGA); Haar Filter; Integer to Integer (Int2Int) Wavelet; Dual Mode Processor

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References


Shet, M.S., Patel, M., Manikantan, K., Ramachandran, S., DWT based feature extraction using Normalized Magnitude based Thresholding and Multilevel Illumination Normalization for enhanced Face Recognition, (2012) International Review on Computers and Software (IRECOS), 7 (5), pp. 1969-1985.

G. Mallat, “A Theory for Multiresolution Signal Decomposition: The Wavelet Representation,” IEEE Trans. Pattern Analysis and Machine Intelligence, vol. II, no. 7, pp. 674–693, 1989.

W. Sweldens, “The Lifting Scheme: A Custom-Design Construction of Biorthogonal Wavelets,” Applied and Computational Harmonic Analysis, vol. 3, no. 2, pp. 186–200, Apr. 1996.

Wang, L., Li, D., Yang, Z., Fault diagnosis of hydrogen-fueled engine using lifting wavelet packet transform, (2012) International Review on Computers and Software (IRECOS), 7 (2), pp. 862-868.

J. Pang and S. Chauhan, “FPGA design of speech compression by using discrete wavelet transform,” in Proceedings of the World Congress on Engineering, WCECS, 2004, pp. 22–24.

J. Altermann, E. Costa, and S. Almeida, “High performance Haar Wavelet transform architecture,” in 2011 20th European Conference on Circuit Theory and Design (ECCTD), 2011, pp. 596–599.

D. Dia, M. Zeghid, and T. Saidani, “Multi-level discrete wavelet transform architecture design,” Proceedings of the World Congress on Engineering, vol. I, pp. 1–5, 2009.

Z. Bo, S. Rong, and W. Qun, “Implementation of Haar Transform with PDDA Architecture for Flexible Scales,” 2009 Second International Conference on Intelligent Computation Technology and Automation, pp. 617–620, 2009.

K. Kuzume, K. Niijima, and S. Takano, “FPGA-based lifting wavelet processor for real-time signal detection,” Signal Processing, vol. 84, no. 10, pp. 1931–1940, Oct. 2004.

P. Chen, “VLSI implementation for one-dimensional multilevel lifting-based wavelet transform,” IEEE Transactions on Computers, vol. 53, no. 4, pp. 386–398, Apr. 2004.

D. Varugheese and N. Muniraj, “FPGA Implementation of New Adaptive DWT-IDWT Lifting Technique for OFDM,” European Journal of Scientific Research, vol. 75, no. 1, pp. 92–103, 2012.

W. Zhang, Z. Jiang, Z. Gao, and Y. Liu, “An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 3, pp. 158–162, Mar. 2012.

S. Lina and G. Guangchun, “Hardware realization and optimized of lifting wavelet transform,” The 2nd International Conference on Information Science and Engineering, pp. 5131–5134, Dec. 2010.

W. Chao and C. A. O. Peng, “Efficient Architecture for 2-Dimensional Discrete Wavelet Transform with Novel Lifting Algorithm,” Chinese Journal of Electronics, vol. 19, no. 1, pp. 1–6, 2010.

H. Liao, M. Mandal, and B. Cockburn, “Efficient architectures for 1-D and 2-D lifting-based wavelet transforms,” IEEE Trans. on Signal Processing, vol. 52, no. 5, pp. 1315–1326, 2004.

B. Wu, S. Member, C. Lin, and S. Member, “A High-Performance and Memory-Efficient Pipeline Wavelet Transform of JPEG2000 Codec,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 12, pp. 1615–1628, 2005.

C. Huang, P. Tseng, and L. Chen, “Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform,” IEEE trans Signal Processing., vol. 2, pp. 2–5, 2004.

K. Andra, C. Chakrabarti, and T. Acharya, “A VLSI architecture for lifting-based forward and inverse wavelet transform,” IEEE Transactions on Signal Processing, vol. 50, no. 4, pp. 966–977, 2002.

G. Shi, W. Liu, L. Zhang, and F. Li, “An Efficient Folded Architecture for Lifting-Based Discrete Wavelet Transform,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 4, pp. 290–294, Apr. 2009.

M. E. Angelopoulou, K. Masselos, P. Y. K. Cheung, and Y. Andreopoulos, “Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs,” Journal of Signal Processing Systems, vol. 51, no. 1, pp. 3–21, Oct. 2007.

C. Desmouliers, E. Oruklu, and J. Saniie, “Discrete wavelet transform realisation using run-time reconfiguration of field programmable gate array (FPGA)s,” IET Circuits, Devices & Systems, vol. 5, no. 4, p. 321, 2011.

S. M. Aziz and D. M. Pham, “Efficient parallel architecture for multi-level forward discrete wavelet transform processors,” Computers & Electrical Engineering, vol. 38, no. 5, pp. 1325–1335, Sep. 2012.

D. L. Fugal, Conceptual Wavelets in Digital Signal Processing. Space & Signals Technical Publishing, 2009, pp. 31–34.


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