A Distributed Parallel Pipelined Hardware-Level Barrier Synchronization Method for Mesh-Connected Multicomputers

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In the article, the authors present a new distributed hardware-level method for barrier synchronization of parallel programs in a mesh-connected multicomputer, which is based on the usage of a virtual multislice pipeline coordinating environment timed by clock pulse waves.
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Mesh-Connected Multicomputer; Parallel Processes; Barrier Synchronization; Hardware-Level Barrier

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T. S. Axelrod, Effects of synchronization barriers on multiprocessor performance, Parallel Computing. n. 3, pp. 129-140, 1986.

MPI: A Message-Passing Interface Standard, Version 3.0 / Message Passing Interface Forum. September 21, 2012 // http://www.mpi-forum.org/docs/docs.html

D. Tsafrir, D. G. Feitelson, Barrier synchronization on a loaded SMP using two-phase waiting algorithms, Proc. Int’l Parallel Distrib. Processing Symp., pp. 80-87, 2002.

J. Li, J. F. Martinez, M. C. Huang, The thrifty barrier: energy-aware synchronization in shared-memory multiprocessors, Proc. 10th Int’l Symp. High Performance Computer Architecture, pp. 14-23, 2004.

N.-T. Tzeng, B. Kasula, Wu Hongyi, Efficient barrier synchronization on wireless computing systems, Proc. 11th Int’l Conf. Paral. Distrib. Systems, pp. 782-788, 2005.

S. Moh, C. Yu, B. Lee, H. Y. Youn, D. Han, D. Lee, Four-ary tree-based barrier synchronization for 2D meshes without nonmember involvement, IEEE Trans. Comput., Vol. 50, n. 8, pp. 811-823, 2001.

T. Hindam, Connecting the distributed hardware agents for barrier synchronization operation, Proc. Int’l Conf. Electrical, Electronic and Computer Engineering, pp. 261-264, 2004.

J. Sampson, R. González, J.-F. Collard, N. P. Jouppi, M. Schlansker, B. Calder, Exploiting fine-grained data parallelism with chip multiprocessors and fast barriers, Proc. 39th Annual IEEE/ACM Int’l. Symp. Microarchitecture, pp. 235-246, 2006.

M. Delgado, S. Kofuji, A distributed barrier synchronization solution in hardware for 2D-mesh multicomputers, Proc. 3rd Int’l Conf. High Performance Computing, pp. 368-373, 1996.

V. Ramakrishnan, I. D. Scherson, R. Subramanian, Efficient techniques for nested and disjoint barrier synchronization, J. Paral. Distrib. Comput., Vol. 58, n. 8, pp. 333-356, 1999.

W. E. Cohen, D. W. Hyde, R. K. Gaede, An optical bus-based distributed dynamic barrier mechanism, IEEE Trans. Comput., Vol. 49, n. 12, pp. 1354-1365, 2000.

T. A. Johnson, R. R. Hoare, Cyclical cascade chains: a dynamic barrier synchronization mechanism for multiprocessor systems, Proc. 15th Int’l Paral. Distrib. Processing Symp., pp. 2061-2068, 2001.

I. V. Zotov, Distributed virtual bit-slice synchronizer: a scalable hardware barrier mechanism for n-dimensional meshes, IEEE Trans. Comput., Vol. 59, n. 9, pp. 1187-1199, 2010.

Abu-Ein, A.A.-K.H., Zotov, I.V., Hatamleh, H.M.A.M., Skopin, D.E., Distributed barrier synchronization procedure with the dynamic limitation of the coordinating signal propagation area, (2012) International Review on Computers and Software (IRECOS), 7 (3), pp. 991-995.

Al-Azzeh, J.S., Review of methods of distributed barrier synchronization of parallel processes in matrix VLSI systems, (2013) International Review on Computers and Software (IRECOS), 8 (4), pp. 927-932.

Connection machine CM-5 technical summary, Thinking Machines Corp., Nov. 1992.

D. K. Panda, Fast barrier synchronization in wormhole k-ary n-cube networks, Proc. First IEEE Symp. High-Performance Computer Architecture, pp. 200-209, 1995.


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