Memory Based Hardware Efficient Implementation of FIR Filters


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Abstract


Finite impulse response (FIR) digital filters are key components used in many digital signal processing (DSP) systems because of their linear phase, stability, fewer finite precision errors and regular structure. The real time realization of FIR filter with less hardware requirement and less latency has become very critical with increasing developments in very large scale integration (VLSI) technology. The objective of this paper to explore the current trends in the development of algorithms and architectures for memory based realization of FIR filters that are mainly concerned with reducing the overall area-delay-power complexities. The purpose of this study is to compare these architectures based on ROM size, delay and throughput. The results presented here would assist the researchers in the field of Digital Signal processing to select best architecture for an application based on requirements. New algorithms and architectures need to be developed to design area-delay-power-efficient FIR filters for various demanding DSP applications.
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Keywords


Finite Impulse Response Filter; Field Programmable Gate Arrays (FPGA); Application Specific Integrated Circuit (ASIC); Distributed Arithmetic (DA); Lookup Table (LUT)

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