A Multiplier-Less Lifting Scheme Based DWT Structure


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Abstract


The merits of Discrete Wavelet Transform (DWT) over other traditional transforms have led to tremendous focus on the applications of Wavelet Transforms. This leads to the requirement for developing a hardware efficient VLSI implementation of the DWT along with low power consumption. In this paper, DWT architecture based on lifting scheme is considered with suitable modifications to the architecture by adopting low power techniques, which contributes to hardware efficient and low power implementation. A shift-add multiplier with signed floating point consideration is used to construct a 2D-DWT lifting based architecture. This proposed multiplier eliminates the use of power consuming costly conventional multipliers. The proposed multiplier represents the signed floating point results which is the drawback of representation in Verilog implementation .A Verilog model is designed and synthesized for the proposed architecture.  The synthesis results indicate that Xilinx vertix-4 FPGA implementation of the proposed technique is demonstrated which achieves Multiplier less structure, 12% reduced number of slices and 10% reduced power architecture compared with conventional one level lifting 2D-DWT architecture using 9/7 Filter
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Keywords


DWT; Lifting Scheme; Signed Floating Point Shift-Add Multiplier; VLSI; Xilinx

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References


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