A Multiplier-Less Lifting Scheme Based DWT Structure

(*) Corresponding author

Authors' affiliations

DOI's assignment:
the author of the article can submit here a request for assignment of a DOI number to this resource!
Cost of the service: euros 10,00 (for a DOI)


The merits of Discrete Wavelet Transform (DWT) over other traditional transforms have led to tremendous focus on the applications of Wavelet Transforms. This leads to the requirement for developing a hardware efficient VLSI implementation of the DWT along with low power consumption. In this paper, DWT architecture based on lifting scheme is considered with suitable modifications to the architecture by adopting low power techniques, which contributes to hardware efficient and low power implementation. A shift-add multiplier with signed floating point consideration is used to construct a 2D-DWT lifting based architecture. This proposed multiplier eliminates the use of power consuming costly conventional multipliers. The proposed multiplier represents the signed floating point results which is the drawback of representation in Verilog implementation .A Verilog model is designed and synthesized for the proposed architecture.  The synthesis results indicate that Xilinx vertix-4 FPGA implementation of the proposed technique is demonstrated which achieves Multiplier less structure, 12% reduced number of slices and 10% reduced power architecture compared with conventional one level lifting 2D-DWT architecture using 9/7 Filter
Copyright © 2014 Praise Worthy Prize - All rights reserved.


DWT; Lifting Scheme; Signed Floating Point Shift-Add Multiplier; VLSI; Xilinx

Full Text:



UshaBhanu.N and Dr.A.Chilambuchelvan, "A Detailed Survey on VLSI Architectures for Lifting based DWT for efficient hardware implementation," International Journal of VLSI design & Communication Systems, Vol.3, Issue: 2, 2012.

Tracy C. Denk and Keshab K. Parhi, "VLSI Architectures for Lattice Structure Based Orthonormal Discrete Wavelet Transforms," IEEE Transactions On Circuits and Systems—II: Analog And Digital Signal Processing, Vol. 44, Issue: 2, February 1997.

Tyler J. Moeller, "Field Programmable Gate Arrays for Radar Front-End Digital Signal Processing," Massahusett's Institute Of Technology, May 22, 1999.

C. Chandrasekhar& Dr. S. Narayana Reddy, "Dynamic Power Reduction in Modified Lifting Scheme Based DWT for Image Processing," Global Journal of Researches in Engineering, Electrical and Electronics Engineering, Vol.12, Issue: 8, 2012.

D. U. Shah, C. H. Vithlani, "Efficient Implementation Of Discrete Wavelet Transforms Using FPGAs," International Journal of Advances in Engineering & Technology, Sept 2011.

DhahaDia, MedienZeghid, TaoufikSaidani, Mohamed Atri, BelgacemBouallegue, Mohsen Machhout and RachedTourki, "Multi-level Discrete Wavelet Transform Architecture Design," Proceedings of the World Congress on Engineering, Vol.1, 2009.

Maria E. Angelopoulou and Peter Y. K. Cheung, "Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs," Journal of VLSI Signal Processing, 2007.

Chao-Tsung Huang, Po-Chih Tseng, and Liang-Gee Chen, Fellow, IEEE, "Flipping Structure: An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform," IEEE Transactions On Signal Processing, Vol.52, Issue: 4, 2004.

Sayed Ahmad Salehi, Saeed Sadri, “Investigation of Lifting-Based Hardware Architectures for Discrete Wavelet Transform,” Circuits, Systems & Signal Processing, Vol.28, Issue: 1, pp 1-16,2009.

Basant K. Mohanty, AnuragMahajan and Pramod K. Meher, “Area and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-D DWT,” IEEE Transactions on Circuit and System-II: Express Brief, vol.59, Issue: 7, pp:434-438, 2012.

Wei Zhang, Zhe Jiang, ZhiyuGao, and Yanyan Liu, “An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform,” IEEE Transactions on Circuits and Systems-II: Express Briefs, vol.59, Issue:3, 2012.

AmitAcharyya, KoushikMaharatna, Bashir M. Al-Hashimi, and Steve R. Gunn, "Memory Reduction Methodology for Distributed-Arithmetic-Based DWT/IDWT Exploiting Data Symmetry," IEEE Transactions On Circuits and Systems—II: Express Briefs, Vol.56, Issue: 4, 2009.

V. Sudhakar, N.S. Murthy, L. Anjaneyulu, "Area Efficient Pipelined Architecture For Realization of FIR Filter Using Distributed Arithmetic,"International Conference on Industrial and Intelligent Information IPCSIT vol.31, 2012.

M. Nagabushanam and S. Ramachandran, “Fast Implementation of Lifting Based DWT Architecture for Image Compression,” Global Journal of Computer Science and Technology Graphics & Vision, Vol.12, Issue: 11, 2012.

Srikanth.S, M.Jagadeeswari, "High Speed VLSI Architecture for Multilevel Lifting 2-D DWT Using MIMO," International Journal of Soft Computing and Engineering, Vol.2, Issue: 2, 2012.

A. Mansouri, A. Ahaitouf, and F. Abdi, "An Efficient VLSI Architectureand FPGA Implementation of High-Speed and Low Power 2-D DWT for (9, 7) Wavelet Filter," International Journal of Computer Science and Network Security, Vol.9 Issue: 3, 2009.

Vijay Krishna Sola and Cyril Prasanna Raj, "Design and Implementation of Parallel and Pipelined Distributive Arithmetic based Discrete Wavelet Transform IP Core," SASTECH, Vol. V, Issue: 2, 2006.

Chih-Hsien Hsia, Jing-Ming Guo , Jen-Shiun Chiang “Improved Low-Complexity Algorithm for 2-D Integer Lifting-Based Discrete Wavelet Transform Using Symmetric Mask-Based Scheme,” IEEE Transactions on Circuits and Systems for Video Technology, Vol.19, Issue: 8, pp: 1202 – 1208, 2009.

M. MounikaVaralakshmi, G.Sravya, "Innovation on a Memory Based Multiplier," International Journal of Engineering Research and Applications (IJERA), Vol.2, Issue: 2, pp:1472-1476, 2012.

TinkuAcharya and ChaitaliChakrabarti, "A Survey on Lifting-based Discrete Wavelet Transform Architectures," Journal of VLSI Signal Processing, vol.42, pp: 321–339, 2006.

Anitha.K, Dr.Dharmistan.K.Varugheese&DrN.J.R.Muniraj, "Modified Lifting Based DWT/IDWT Architecture for OFDM on Virtex-5 FPGA," Global Journal of Researches in Engineering, Electrical and Electronics Engineering, Vol.12, Issue: 8, 2012.

Ali M. Al-Haj, "Fast Discrete Wavelet Transformation Using FPGAs and Distributed Arithmetic," International Journal of Applied Science and Engineering, Vol.1, Issue: 2, pp: 160-171, 2003.

Mehboob Alam, WaelBadawy, VassilDimitrov and Graham Jullien, "An Efficient Architecture for a Lifted 2D Biorthogonal DWT," Journal of VLSI Signal Processing,Vol.40, pp: 335–342, 2005.

Po-Chih Tseng, Chao-Tsung Huang, and Liang-Gee Chen, "VLSI implementation of shape-adaptive discrete wavelet transform," Visual Communications and Image ProcessingProceedings of SPIE, Vol. 4671, 2002.

JiajiWua, Zhensen Wu and Chengke Wu, "Lossy to lossless compressions of hyperspectral images using three-dimensional set partitioning algorithm," Electronic Imaging and Multimedia Technology IVProc. of SPIE, Vol. 5637, 2005.

Chin-Fa Hsieh, Tsung-Han Tsai, Neng-Jye Hsu, Chih-Hung Lai, " A Novel, Efficient Architecture for the 1D, Lifting-Based DWT with Folded and Pipelined Schemes," in Proc. JCIS, 2006.

Ali M. Al-Haj, "An FPGA-Based Parallel Distributed Arithmetic Implementation of the 1-D Discrete Wavelet Transform," Informatica 29, pp: 241–247, 2005.

Sami Khawam, TughrulArslan, and Fred Westall, "Synthesizable Reconfigurable Array Targeting Distributed Arithmetic for System-on-Chip Applications,"Parallel and Distributed Processing Symposium, 2004.

Aloui, N., Talbi, M., Cherif, A., The optimized wavelet filters and real-time implementation of speech codec base on DWT n TMS320C64xx, (2013) International Review on Computers and Software (IRECOS), 8 (2), pp. 454-462.

Alirr, O., Jumari, K., Digital Image Watermarking and Encryption Using DWT and RSA, (2013) International Review on Computers and Software (IRECOS), 8 (4), pp. 958-963.


  • There are currently no refbacks.

Please send any question about this web site to info@praiseworthyprize.com
Copyright © 2005-2024 Praise Worthy Prize