A Low Power Design of Single Precision Floating Point Multiplier for Computing Techniques


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Abstract


A design and implementation of a 32 bit fast floating point multiplier with the single precision IEEE 754-2008 standard target for Xilinx virtex-5 FPGA. The proposed design and timing information of the multiplier sub-module has been calculated and the proposed design intends to increase the speed on the multiplier by reducing delay at every stage using optimal adder design. The proposed multiplier is made to multiply two floating point numbers and generate the output to make minimum time delay. The modules have been written in verilog HDL and it is simulated using the Xilinx ISE12.1 targeted on the FPGA.
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Keywords


Floating Point; FPGA; Multiplication

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References


IEEE standards broad, IEEE standard for floating-point arithmetic,2008.

Paschalakis .S, Lee .P, “Double precision floating-point Arithmetic on FPGAs”, IEEE/ International conference on field programmable technology–FPT’03, Tokyo, Japan. PP:352-358,2003.

B. Fagin and C. Renard, “Field Programmable Gate Arrays and Floating Point Arithmetic,” IEEE Transactions on VLSI, vol. 2, no. 3, pp. 365– 367, 1994'.

Hasan Krad and Aws Yousif Al-Taie, “Performance Analysis of a 32-Bit Multiplier with a Carry-Look-Ahead Adder and a 32-bit Multiplier with a Ripple Adder using VHDL”, Journal of Computer Science 4 (4): 305-308, 2008.

A. Jaenicke and W. Luk, "Parameterized Floating-Point Arithmetic on FPGAs", Proc. of IEEE ICASSP, 2001, vol. 2, pp. 897-900.

Hamid L.S.A, Shehata.K, El-Ghitani.H, Elsaid.M, “Design of Generic floating point multiplier and Addder/subtractor units”, International conference on computer modelling and simulation”, 2010, pp:615-618.

Hamid, L.S.A., Shehata, K., El-Ghitani,H., ElSaid,M.,"Design of Generic Floating Point Multiplier and Adder/Subtractor Units" , 12'h International Conference on Computer modelling and Simulation, 2010, pp.615-618.


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