A Low Power Design of Single Precision Floating Point Multiplier for Computing Techniques
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A design and implementation of a 32 bit fast floating point multiplier with the single precision IEEE 754-2008 standard target for Xilinx virtex-5 FPGA. The proposed design and timing information of the multiplier sub-module has been calculated and the proposed design intends to increase the speed on the multiplier by reducing delay at every stage using optimal adder design. The proposed multiplier is made to multiply two floating point numbers and generate the output to make minimum time delay. The modules have been written in verilog HDL and it is simulated using the Xilinx ISE12.1 targeted on the FPGA.
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