An Efficient 2DWT-A Architecture Using Distributive Arithmetic Algorithm
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The previous paper presents a 2DWT-A algorithm an efficient architectures for real time signal processing, architecture exploits both row-wise and column-wise parallelism in the direct implementation and processing was scheduled by carefully pipelining the lifted steps. Our work is an important part of developing new hardware efficient methods for the implementation of DWT through Distributed Arithmetic (DA) method. We implement the parallel DA for row wise convolution and for column-wise lifting, the parallel-pipelined lifting scheme using polyphase DA decomposition. The significance of this paper is to propose an efficient architecture for real time, low power application and hardware implementation based on DA method. The various architectures are analyzed in terms of hardware and timing complexity. This study is useful for deriving an efficient method for improving the speed, power consumption and hardware complexities of existing architectures and to design a new hardware implementation of 2DWT-A using DA based parallel-pipelined lifting schemes. Our implementation achieves, effective hardware utilization using polyphase DA method, low power consumption with reduction in multipliers and use of look-up table (LUT) and high speed performance with the help of Parallel DA method.
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