Genetic Algorithm Based Optimization of Vertical Links for Efficient 3D NoC Multicore Crypto Processor


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Abstract


The applications of network on chip has become wide. However the implementation of 3D NoC has become a vital issue with the fabrication of TSV. Hence, this work focuses on the means of reducing the number of vertical links in order to reduce the TSV. The optimum number of vertical for a given 3D mesh NoC is modeled as an optimization problem. The optimum number of vertical links is mapped using Genetic Algorithm to the given 3D mesh. The improvement in throughput and latency has been observed for synthetic traffic and real time benchmarks in comparison with the Simulated Annealing methodology. A 3D routing is proposed for the above vertical link optimized 3D NoC topology considering the congestion. The proposed routing has been compared with XY routing for 3D mesh NoC for synthetic and real time benchmarks. The performance in terms of throughput and latency was improved for GA based mapping with proposed routing.
It is applied for the design of a 3D NoC based multicore crypto processor design for cloud computing. It should be noted that there is an improvement in the execution times for the RC6 and AES algorithms for varying key size with and without NoC. The benchmark application AES256 shows an improvement of 49% with NoC and RC6128 is close by 44.7%. The throughput improvement is 52% for RC6 and Blowfish by 48%.


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Keywords


Through Silicon Via (TSV); System-On-A-Chip (SOC); Network On Chip (Noc); Genetic Algorithm (GA); Simulated Annealing (SA)

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