High Performance and Reliable Fault Detection Scheme for the Advanced Encryption Standard


(*) Corresponding author


Authors' affiliations


DOI's assignment:
the author of the article can submit here a request for assignment of a DOI number to this resource!
Cost of the service: euros 10,00 (for a DOI)

Abstract


Fault injection attacks are powerful cryptanalysis techniques against the Advanced Encryption Standard (AES) algorithm. These attacks are based on injecting faults into the structure of the AES to obtain confidential information. To protect the AES implementation against these attacks, a number of countermeasures have been proposed. In this paper, we proposed a fault detection scheme, based on the information redundancy, for the AES. We discuss the strengths and the weaknesses of this scheme against the fault attacks. Moreover, we conduct a comparative study between fault detection schemes from the literature in terms of fault detection capabilities and implementation cost. The simulation results show that the fault coverage achieves 99.998% for the proposed scheme. Moreover, the proposed detection scheme has been implemented on Xilinx Virtex-5 FPGA. Its fault coverage, area overhead, throughput and frequency degradation have been compared and it is shown that the proposed scheme allows a trade-off between the hardware overhead and the security of the AES.
Copyright © 2013 Praise Worthy Prize - All rights reserved.

Keywords


Security; Differential Fault Analysis (DFA); Fault Attacks; Fault Detection Schemes; Countermeasures; Advanced Encryption Standard (AES)

Full Text:

PDF


References


National Institute of Standards and Technology (NIST), Advanced Encryption Standard (AES), FIPS Publication 197, http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf, 2001.

H. Mestiri, M. Machhout, R. Tourki, Performances of the AES design in 0.18µm CMOS technology, IEEE, 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2012.

A. Moh'd, Y. Jararweh and L. Tawalbeh, AES-512: 512-bit Advanced Encryption Standard algorithm design and evaluation, 7th International Conference on Information Assurance and Security (IAS 2011), pp. 292-297, 2011.

N. Benhadjyoussef, W. Elhadjyoussef, M. Machhout, K. Torki, R. Tourki, A cryptographic processor for 32 bit embedded system with resource constraints, (2013) International Review on Computers and Software (IRECOS.) 8 (1), pp. 132-143.

C. Giraud, DFA on AES, In H. Dobbertin, V. Rijmen, A. Sowa (Eds.): Advanced Encryption Standard, Springer-Verlag Berlin Heidelberg, LNCS. 3373, pp. 27–41, 2005.

P. Dusart, G. Letourneux, and O. Vivolo, Differential Fault Analysis on A.E.S, In J. Zhou, M. Yung, Y. Han (Eds.), Applied Cryptography and Network Security, Springer-Verlag Berlin Heidelberg, LNCS. 2846, pp. 293-306, 2003.

G. Piret and, J.J. Quisquater, A Differential Fault Attack Technique against SPN Structures, with Application to the AES and Khazad, In C.D. Walter et al. (Eds.), Cryptographic Hardware and Embedded Systmes, Springer-Verlag Berlin Heidelberg, LNCS. 2779, pp.77-88, 2003.

A. Moradi, M.T. Manzuri Shalmani, and M. Salmasizadeh, A Generalized Method of Differential Fault Attack Against AES Cryptosystem, In L. Goubin and M. Matsui (Eds.), Cryptographic Hardware and Embedded Systems, LNCS. 4249, pp. 91-100, 2006.

J. Takahashi, T. Fukunaga, K. Yamakoshi, DFA Mechanism on the AES Key Schedule, In IEEE computer society, editor, Workshop on Fault Diagnosis and Tolerance in Cryptography, pp. 62 – 74, FDTC 2007.

M. Tunstall, D. Mukhopadhyay, and S. Ali, Differential Fault Analysis of the Advanced Encryption Standard using a Single Fault, Available from: http://eprint.iacr.org/2009/575.pdf, 2009.

S. Ali1, D. Mukhopadhyay, and M. Tunstall, Differential Fault Analysis of AES using a Single Multiple-Byte Fault, Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), pp. 35-42, 2011.

D. Boneh, R.A. DeMillo, R.J. Lipton, On the importance of checking cryptographic protocols for faults, Advances in Cryptology, EUROCRYPT 1997, LNCS. 1233, pp. 37-51, 1997.

M. Joye, P. Manet, and J.B. Rigaud, Strengthening Hardware AES Implementations Against Fault Attacks, IET Information Security, pp. 106-110, Sept, 2007.

G.D. Natale, M.L. Flottes, B. Rouzeyre, On-Line Self-Test of AES Hardware Implementations, DSN'07, Workshop on Dependable and Secure Nanocomputing, Edinburgh, Royaume-Uni, 2007.

T.G. Malkin, F.-X. Standaert, and M. Yung, A Comparative Cost/Security Analysis of Fault Attack Countermeasures, In L. Breveglieri et al. (Eds.), Fault Diagnosis and Tolerance in Cryptography, Springer-Verlag Berlin Heidelberg, LNCS. 4236, pp. 159-172, 2006.

K.Wu, R. Karri, G. Kuznetsov, and M. Goessel, Low Cost Concurrent Error Detection for the Advanced Encryption Standard, Proceedings of International Test Conference, pp. 124 -1248, 2004.

C. Yen, and B. Wu, Simple Error Detection methods for Hardware Implementation of Advanced Encryption Standard, IEEE Transactions on Computers, Vol. 55, N°. 6, June 2006.

M. Mozaffari-Kermani, and A. Reyhani-Masoleh, Concurrent Structure-Independent Fault Detection Schemes for the Advanced Encryption Standard, IEEE Transactions on Computers, Vol. 59, pp. 608-622, 2010.

J. Rajendran, H. Borad, S. Mantravadi, R. Karri, SLICED: Slide-Based Concurrent Error Detection Technique for Symmetric Block Ciphers, IEEE International Symposium on Hardware-Oriented Security and Trust, pp. 70-75, 2010.

J. Chu, M. Benaissa, Error Detecting AES Ysing Polynomial Residue Number Systems, Microprocessors and Microsystems, Elsevier, 2012.

C.N. Zhang, Q. Yu, and X.W. Liu, A Hybrid Fault Tolerant Approach for AES, International Journal of Network Security, vol.15, No.1, pp.263-269, 2013.

G.Di Natale, M.L. Flottes, B. Rouzeyre, A Novel Parity Bit Scheme for SBox in AES Circuits, IEEE Design and Diagnostics of Electronic Circuits and Systems, 2007.

A.Satoh, T. Sugawara, N. Homma, T. Aoki, High-Performance Concurrent Error Detection Scheme for AES Hardware, In E. Oswald and P.Rohatgi (Eds), Cryptographic Hardware and Embedded System, LNCS. 5154, pp. 100-112, 2008.

M.H. Sargolzaie, Low Cost Fault Tolerant Architecture for Advanced Encryption Standard, Canadian Journal on Electrical and Electronics Engineering, vol. 2, No. 9, pp. 427-432, 2011.

X. Guo, D. Mukhopadhyay, and R. Karri, Provably Secure Concurrent Error Detection Against Differential Fault Analysis, IACR Cryptology ePrint Archive, Available from:eprint.iacr.org/2012/552.pdf, 2012.


Refbacks

  • There are currently no refbacks.


Please send any question about this web site to info@praiseworthyprize.com
Copyright © 2005-2024 Praise Worthy Prize