A VLSI Based Framework for Iterative and Adaptive Based Image Filter for Impulse Noise Removal

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Implementation of noise removal filter in a VLSI domain is important. As VLSI domain is suitable for image processing applications and most of the image processors are now replaced with high performance FPGA. The inbuilt memory (Block RAM and distributed RAM) available in the FPGA fabric are utilized to store a pixel window of considerable size. In this paper the authors propose a VLSI based framework for efficient implementation of the Adaptive maximum pixel based Noise detector (APMAD) based filters. The histogram calculation of the image is efficiently carried out using the existing memory in the FPGA and using the “read first” property of the FPGA RAM, a single pixel requires two clocks for updating the histogram. As the proposed algorithm is adaptive and iterative, only FPGA with rich internal memory (RAM) should be chosen as the utilization of external memory will add additional latency. The proposed algorithm is simulated in FPGA (XILINX 12.2 ISIM) environment. Performance evaluation of noise detector are calculated in terms of PFP and PFN and quantitative evaluation of the filter are measured viz PSNR and MSE.
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Impulse Noise; Noise Removal Filter; Field Programmable Gate Array; Histogram

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