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FPGA Implementation of Baseband OFDM Transmitter and Receiver Using Modified IFFT/FFT to Reduce Latency
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Abstract
The key component of any OFDM system is the IFFT/FFT block; moreover it is the most computationally complex block. In order to support 4G standard specified speeds, in mobile handheld devices it is necessary to reduce the computational complexity and the time taken to perform IFFT/FFT functions. The IFFT/ FFT block in the transmitter/ receiver is preceded by a serial to parallel convertor; the latency in this conversion is reduced by a novel approach. This approach presented in this paper modifies the radix-2 FFT algorithm, by evaluating the contribution by every complex input to every output on its arrival. This reduction in the latency is carried forward by allowing the outputs of IFFT/FFT block to stream out even as concurrent outputs are being calculated. In order to analyse the reduction in the complexity of the OFDM system using this approach, it is simulated for a target Xilinx device using Verilog HDL. It was observed that the device utilization was significantly reduced.
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References
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