FPGA Implementation of Baseband OFDM Transmitter and Receiver Using Modified IFFT/FFT to Reduce Latency

(*) Corresponding author

Authors' affiliations

DOI's assignment:
the author of the article can submit here a request for assignment of a DOI number to this resource!
Cost of the service: euros 10,00 (for a DOI)


The key component of any OFDM system is the IFFT/FFT block; moreover it is the most computationally complex block.  In order to support 4G standard specified speeds, in mobile handheld devices it is necessary to reduce the computational complexity and the time taken to perform IFFT/FFT functions. The IFFT/ FFT block in the transmitter/ receiver is preceded by a serial to parallel convertor; the latency in this conversion is reduced by a novel approach.  This approach presented in this paper modifies the radix-2 FFT algorithm, by evaluating the contribution by every complex input to every output on its arrival.  This reduction in the latency is carried forward by allowing the outputs of IFFT/FFT block to stream out even as concurrent outputs are being calculated.  In order to analyse the reduction in the complexity of the OFDM system using this approach, it is simulated for a target Xilinx device using Verilog HDL.  It was observed that the device utilization was significantly reduced.
Copyright © 2013 Praise Worthy Prize - All rights reserved.


Accumulator; FFT; IFFT; Symbol Combiner

Full Text:



Koushik Maharatna, Eckhard Grass, Ulrich Jagdhold, A 64 point Fourier Transform Chip for High speed Wireless Lan Application using OFDM IEEE, Journal of Solid State Circuits, Vol.39, No.3.

Shen Jui Huang, Sau Gee Chen A High throughput Radix-16 FFT processor with parallel and Normal input/output ordering for IEEE 802.15.3c (WPANS) systems, IEEE transactions on Circuits and systems I: regular papers.

Haining Jiang, Hanwen Luo, Jifeng Tian and Wentao Song, Design of an efficient FFT processor for OFDM systems, IEEE transactions on consumer electronics, Vol. 51, No. 4.

Xuan Guan, Yunsi Fei, Hai Lin Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Le Jin, Lin Liang, A power-of-two FFT algorithm and structure for DRM receiver, IEEE transactions on Consumer Electronics.

Vennila C; Palaniappan C T K; Krishna K V; Lakshminarayanan G; Seok Bum Ko, Dynamic partial reconfigurable FFT/IFFT pruning for OFDM based Cognitive radio, IEEE International Symposium on Circuits and Systems,

Khan M N; Mohamed Ismail; Jawahar P K, A efficient FFT/IFFT architecture for wireless communication, International conference on Communications and Signal Processing.

Cho. T; Lee H, A High speed low complexity Modified Radix 25 FFT processor for High Rate WPAN application, IEEE transactions on VLSI.

Kang, Byungcheol; Kim, Jaeseok, Low complexity multi-point 4 channel FFT processor for IEEE802.11n MIMO OFDM WLAN system, International Conference on Green and Ubiquitous Technology.

Yin-Tsung Hwang, Sung-Jun Tsai, Yi-Yo Chen Design and implementation of an optical OFDM baseband receiver in FPGA, International Symposium on VLSI design Automation and Test.

Kiokes G; Economakos G; Amditis A; Uzunoglu N K; Design and Implementation of an OFDM system for Vehicular communications with FPGA technologies, International Conference on Design& Technology of Integrated Systems in Nanoscale Era.

Rajeswari L M; Manocha S K, Design of data adaptive IFFT/FFT block for OFDM system, 2011 Annual IEEE India Conference.

Gautam V; Ray K C; Haddow P, Hardware efficient design of Variable length FFT processor, IEEE International Symposium on Design and Diagnostics of Electronics Circuits and Systems.

Dreschmann M; Meyer J; Hubner M;SchmogrowR; Hillerkuss D; Becker J; Leuthold J; Freude W, Implementation of an ultra high speed 256 point FFT for Xilinx Virtex 6 devices, IEEE conference on Industrial Informatics.

S. Reza Talebiyan, Saied Hosseini-Khayat, Delay Analysis of Pipeline FFT Processors, (2009) International Review on Computers and Software (IRECOS), 4 (3), pp.422-425.

M. Arioua, S. Belkouch, M. M’rabet Hassani, Efficient 64-Point FFT/IFFT Processor Based on 8-Point FFT Module for OFDM Based WLAN, (2012) International Review on Computers and Software (IRECOS), 7 (1), pp. 92-99.

Konstantinos B. Baltzis, Vasileios Goulemes, On the Vulnerability of OFDM Systems to Receiver Impairments, (2012) International Review on Computers and Software (IRECOS), 7 (1), pp. 100-105.

Amir Safaei, Binary Implementation of Parallel Ternary Full Adder and Subtractor, (2012) International Review on Computers and Software (IRECOS), 7 (2), pp. 495-498.

Amjad N. Jabir, Sabira Khatun, N. K. Noordin, Borhanuddin M. Ali, Lattice-Reduction-Based Detector for Combined OFDM Space Division Multiple Access Wireless System, (2009) International Review on Computers and Software (IRECOS), 4 (1), pp. 119-125.

Mattera, D., Tanda, M., Blind symbol timing and CFO estimation for OFDM/OQAM systems, (2013) IEEE Transactions on Wireless Communications, 12 (1), art. no. 6397549, pp. 268-277.

Mattera, D., Tanda, M., Bellanger, M., Frequency-spreading implementation of OFDM/OQAM systems, (2012) Proceedings of the International Symposium on Wireless Communication Systems, art. no. 6328353, pp. 176-180.


  • There are currently no refbacks.

Please send any question about this web site to info@praiseworthyprize.com
Copyright © 2005-2024 Praise Worthy Prize