A Cryptographic Processor for 32 bit Embedded System with Resource-Constraints

N. Benhadjyoussef(1*), W. Elhadjyoussef(2), M. Machhout(3), K. Torki(4), R. Tourki(5)

(1) Laboratoire d’électronique et micro-électronique (LAB-IT06), Faculté des Sciences de Monastir 5019, Monastir (FSM), Tunisia
(2) Laboratoire d’électronique et micro-électronique (LAB-IT06) Faculté des Sciences de Monastir 5000, Monastir (FSM), Tunisia
(3) Laboratoire d’électronique et micro-électronique (LAB-IT06) Faculté des Sciences de Monastir 5000, Monastir (FSM), Tunisia
(4) Circuits Multi-Project, 46, Avenue Félix VIALLET, 38031 GRENOBLE Cedex, France
(5) Laboratoire d’électronique et micro-électronique (LAB-IT06) Faculté des Sciences de Monastir 5000, Monastir (FSM), Tunisia
(*) Corresponding author


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Abstract


With the information breaches growing nowadays, the demand for serious efforts towards ensuring security in embedded systems becomes more important. The successful employment of these embedded systems for e-commerce, transaction banking, mobile commerce, etc, depend on the reliability of the security solutions. Respecting the real-time performance and the resource-constrained target environment for the next-generation applications, the embedded system design have been a theme of serious study these last few years. This paper presents a hardware crypto-processor for the arising issue of information security in embedded system. This crypto-processor can be used for various security applications such as smartcards, network routers, wireless systems, etc. The proposed 32-bit processor executes various IP crypto cores like hash function, private and public key operations, Random Number generator and other application programs such as user authentication. The hardware description is done in ModelSim using VHDL and synthesized using Synopsys Design Compiler. Furthermore, the proposed crypto-processor is implemented using Xilinx XC5VFX70t FPGA device and an ASIC CMOS 40 nm technology. The results show a high performance, confirming the efficiency of the processor. We have carefully chosen the dedicated algorithms to reduce the required memory resources while respecting the necessary runtime within reasonable limits. The proposed crypto-processor has a total core area of 1.35 mm2 and can achieve an operating system frequency of 500 MHz. The estimated power of the chip was 4,6 mW at 10 MHz.
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Keywords


Embedded System; Cryptographic Processor; AES; ECDSA; ASIC and FPGA Implementation; Low-Resource Constraints

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References


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