A New Design Approach of a Mixed Circuit by Using an Analogical Inverter

A. Zouyed(1*), K. Cheikh(2)

(1) , Algeria
(2) , Algeria
(*) Corresponding author

DOI's assignment:
the author of the article can submit here a request for assignment of a DOI number to this resource!
Cost of the service: euros 10,00 (for a DOI)


This research work concerns a mixed ASIC (Application Specific Integrated Circuit) integrating both analogical and digital functions. The development of this type of integrated circuit is receiving a great deal of interest. In order to solve the difficulties related to the absence of common basic structure necessary to the conception of both types of function, we propose a simple technique based on the use of an inverter NMOS, configured for the analogical treatment. This approach is applied to a mixed circuit, which is a PLL. The comparison of the results obtained through behavioral and structural simulations confirm the interest and the efficiency of such a technique.
Copyright © 2015 Praise Worthy Prize - All rights reserved.


Mixed Circuit; Design; Modeling; Behavioral; Structural; VHDL; SPICE

Full Text:



P.Hirschuer, La conception d’ASIC, Processeurs et systèmes, n°21, pp 21-24, Novembre 88.

H.Chang, E.Liu, E.Felt, A Top-down design methodology for analog Integrated Circuits, Kluwer Academic Publishers, first Edition, 1997.

C.Mead, Conway, Introduction to VLSI systems, Edition Wesley, 1980.

E.Habekotte and B.hoefflinger, State of the art in the analog NMOS circuit design, Proceeding of the IEEE, Vol.75, n°6, pp 816-827, June 1987.

P.R.Gray and R.G.Meyer, Analysis and design of Analog integrated circuits, John Wiley & Sons, New york, NY, USA, 4th edition, 2001.

L.W.Nagel, A Computer Program to Simulate Semi-Conductor Circuits, University California Berkley,Memo UCB/ERL, May 1975.

J.A.Connelly, J.S Pena-Finol, A MOS four quadrant Analog Multiplier using the Quarter Square Technique, IEEE journal solid state circuits,vol.22, no6, December 1987.

P.Choi and J.A.Connelly, Macromodeling with SPICE, Prentice Hall New Jersey 1992.

J.A.Connelly and W.E.Thain, Simulation and modeling an improved VCO macromodel, IEEE, Circuit and Devices Magazine,Vol.8, pp8-16, .July 1992.

P.Yang, The macromodeling of Phase-Locked Loops for SPICE simulation, IEEE Circuits and Devices, pp 11-15, March 1991.

M.Sebeloue, J.Boucher, Behavioral Modeling and Characterization of Basic functions of the analog circuits, European IC-CAP Users Meeting HP – Marseilles June 1999.

B.A.Antao, R.H.Leonowich, Mixed-Mode Simulation of Phase-Locked Loops, IEEE Custom Integrated Circuits Conference 1993.

B.A.Antao, El-Turky, F.M, Behavioral modeling phase-locked loops for mixed-mode simulation, Analog Integrated Circuits and Signal Processing, Vol.10, Kluwer Academic Publishers July 1996.

M. Subert, Mixed-Signal Simulation Event-Driven of a Phase Locked Loop, IEEE BMAS, Orlando, Florida, USA, pp 1-6, October 1999.

Z.Xing, Mixed signal Multilevel Circuit Simulation: An implicit mixed mode solution, IEEE, NTU, EDS, January 2003.

T.Lagutere, J.M.Paillot, H.Guegnaud,, PLL modeling Method for Integration in an IF receiver ASIC, Proceeding of the IEEE International Symposium on Industrial Electronics, pp 199-204, May 2004.

D.H.Wolawer, Phase-Lock loop circuit design, Edition Prentice Hall, Advanced References Serial 1991.

TESS par TESOFT, Personal Computer Tools for Electronic Design.

S.Liu, L.Nagel, Small-Signal MOSFET Models for Analog Circuit Design, IEEE Journal Solid State Circuit,Vol.17, no.6, December 1982.

Alain. Rivat, Logiciel de simulation analogique PSPICE 9.2.


  • There are currently no refbacks.

Please send any question about this web site to info@praiseworthyprize.com
Copyright © 2005-2020 Praise Worthy Prize