Application-oriented Testing of Embedded Processor Cores Implemented in FPGA Circuits

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This paper deals with application-oriented testing methods for FPGA circuits. These methods are useful both for manufacturing testing and the detection of the incorrect behaviour of applications in cases when Single-Event Upset (SEU) phenomena occur. After a brief introduction to the test approaches for the detection of SEU-induced faults in FPGAs, the paper focuses on the problem of testing embedded processor cores, and a new approach to the efficient instruction testing of microprocessor cores is presented.
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Functional Test; Embedded Processor-Core Test; Single-Event Upset; Built-In Self-Test

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R. Katz, K. LaBel, J. J. Wang, B. Cronquist, R. Koga, S. Penzin, and G. Swift, Radiation effects on current field programmable technologies, IEEE Trans. Nucl. Sci., Vol. 44, pp. 1945-1956, 1997.

R. Katz, J. J. Wang, R. Reed, I. Kleyner, M. D'Ordine, J. McCollum, B. Cronquist, and J. Howard, The effects of architecture and process on the hardness of programmable technologies, IEEE Trans. Nucl. Sci., Vol. 46, pp. 1736-1743, 1999.

T.C. May, M.H. Woods, Alpha-particle-induced soft errors in dynamic memories, IEEE Trans. on Electron Devices, Vol. ED-26, n. 1, pp. 2-9, 1979.

E.L. Petersen, P. Shapiro, J.H. Adams, E.A. Burke, Calculation of cosmic-ray induced soft upsets and scaling in VLSI devices, IEEE Trans. on Nuclear Science, Vol. NS-29, n. 6, pp. 2055-2063, 1982.

S. Karp, B.K. Gilbert, Digital system design in the presence of single event upsets, IEEE Trans. on Aerospace and Electronic Systems, Vol. 29, n. 2, pp. 310-316, 1993.

M. Renovell, Y. Zorian, Different experiments in test generation for XILINX FPGAs, Proc. Int’l Test Conf., pp. 854–862, 2000.

C. Stroud, S. Konala, C. Ping, M. Abramovici, Built-in self-test of logic blocks in FPGAs (finally, a free lunch: BIST without overhead), Proc. VLSI Test Symp., pp. 387–392, 1996.

W. Huang, F. Lombardi, An approach to testing programmable/ configurable field programmable gate arrays, Proc. IEEE VLSI Test Symp., pp. 450–455, 1996.

A. Doumar, H. Ito, Testing the logic cells and interconnect resources for FPGAs, Proc. Eighth Asian Test Symp., pp. 369–374, 1999.

M. Renovell, J. Portal, J. Figueras, Y. Zorian, Testing the interconnect of RAM-based FPGAs, IEEE Design and Test of Computers, Vol. 15, n 1, pp. 45–50, 1998.

M. Renovell, J. Figueras, Y. Zorian, Test of RAM-based FPGA: Methodology and application to interconnect, Proc. IEEE VLSI Test Symp., pp. 230–237, 1997.

H. Michinishi, T. Yokohira, T. Okamoto, A test methodology for interconnect structures of LUT-based FPGAs, Proc. IEEE Asian Test Symp., pp. 68–74, 1996.

M. Abramovici, C. Stroud, BIST-based delayfault testing in FPGAs, Proc. Eighth IEEE Int’l On-Line Testing Workshop, pp. 131–134, 2002.

I. Harris, P.Menon, R. Tessier, BIST-based delay path testing in FPGA architectures, Proc. Int’l Test Conf., pp. 932–938, 2001.

M.B. Tahoori, E.J. McCluskey, M. Renovell, P. Faure, A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs, Proc. 22nd IEEE VLSI Test Symposium, 154, 2004.

Li Chen, S.Dey, Software-Based Self-Testing Methodology for Processor Cores, IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 20, n 3, pp. 369-380, 2001.

N.Kranitis, A.Paschalis, D.Gizopoulos, Y.Zorian, Effective Software Self-Test Methodology for Processor Cores, Proc. Design Automation & Test in Europe 2002, Paris, pp. 592-597, 2002.

N.Kranitis, D.Gizopoulos, A.Paschalis, Y.Zorian, Instruction-based self-testing of processor cores, Proc. 20th IEEE VLSI Test Symp., pp. 223-228, 2002.

J. Shen, J. A. Abraham, Native Mode Functional Test Generation for Processors with Applications to Self Test and Design Validation, Proc. International Test Conference, pp. 990-999, 1998.

K.Batcher C.Papachristou, Instruction Randomization Self Test for Processor Cores, Proc. VLSI Test Symp., pp. 34-40, 1999.

L.Chen, S.Dey, DEFUSE: A Deterministic Functional Self-Test Methodology for Processors, Proc. IEEE VLSI Test Symp., pp. 255-262, 2000.

F.Corno, G.Cumani, M.Sonza Reorda, G.Squillero, Fully Automatic Test Program Generation for Microprocessor Cores, Proc. Design Automation & Test in Europe 2003, pp. 1006-1011, 2003.

F.Corno, E.Sanches, M. Sonza Reorda, G.Squillero, Automatic Test Program Generation: A Case Study, IEEE Design and Test of Computers, Vol. 21, n. 2, pp. 102-109, 2004.

M.Rebaudengo, M.Sonza Reorda, M.Violante, A new functional model for FPGA application-oriented testing, Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 372-380, 2002.


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