Open Access Open Access  Restricted Access Subscription or Fee Access

A 12-bit Fine-Coarse Successive Approximation Stochastic Analog to Digital Converter

(*) Corresponding author

Authors' affiliations



The surrounding world is composed of continuous time and amplitude analog signals, such as the sound signal picked by a microphone, the light entering a camera, the temperature measured by a thermocouple. In order to process these real world signals by computers, they have to be converted to digital signals. Rapid advances in media technology require high performance analog to digital converters ADCs. In this work, a 12-bit Successive Approximation Register SAR Stochastic Analog to Digital Converter ADC topology has been designed using complementary metal-oxide-semiconductor CMOS in a 0.35µm technology and a single supply voltage equal to 3.3V. In order to reduce the number conversion loops in a typical SAR ADC. 8-bits of the conversion are performed using the SAR ADC and the remainder is fed to the stochastic ADC. Taking the remainder from the SAR ADC allows the input signal of the stochastic ADC to fall within a limited range. The stochastic ADC performs 4-bit conversion using 512 parallel comparators. Since a large number of comparator is used, a simple single ended comparator has been proposed. The proposed comparator reduces the dissipated power by 38% compared to the conventional single ended comparators for each comparator. The gain of the proposed comparator has doubled compared to the conventional single ended comparator. Using this hybrid conversion also solves the problem of the limited input range for stochastic ADCs. Typical stochastic ADCs have an input range around 1mV, using a SAR ADC in the first stage increased the input voltage range to 3.3 V. The ADC has a sample rate of 50Ms/s. The proposed ADC achieves an SNDR equal to 71.2 dB. The DNL -0.44/+0.47 and INL -0.55/+0.59 LSB.
Copyright © 2022 Praise Worthy Prize - All rights reserved.


Analog-to-Digital-Converter; SAR ADC; Stochastic ADC; Offset Voltage Analysis; Single Ended Comparator; Media Technology

Full Text:



M. Zhu, S. Biswas, S. I. Dinulescu, N. Kastor, E. W. Hawkes and Y. Visell, "Soft, Wearable Robotics and Haptics: Technologies, Trends, and Emerging Applications," in Proceedings of the IEEE, vol. 110, no. 2, pp. 246-272, Feb. 2022.

S. O. Ajakwe, C. I. Nwakanma, D. -S. Kim and J. -M. Lee, "Key Wearable Device Technologies Parameters for Innovative Healthcare Delivery in B5G Network: A Review," in IEEE Access, vol. 10, pp. 49956-49974, 2022.

J. A. Gallud, R. Tesoriero, M. D. Lozano, V. M. R. Penichet and H. M. Fardoun, "The Use of Tangible User Interfaces in K12 Education Settings: A Systematic Mapping Study," in IEEE Access, vol. 10, pp. 24824-24842, 2022.

S. V. Salazar, C. Pacchierotti, X. de Tinguy, A. Maciel and M. Marchal, "Altering the Stiffness, Friction, and Shape Perception of Tangible Objects in Virtual Reality Using Wearable Haptics," in IEEE Transactions on Haptics, vol. 13, no. 1, pp. 167-174, 1 Jan.-March 2020.

P. Kongpark, "A simple Analog to Digital Converter for Capacitive Sensors," 2021 Joint International Conference on Digital Arts, Media and Technology with ECTI Northern Section Conference on Electrical, Electronics, Computer and Telecommunication Engineering, 2021, pp. 124-127.

K. L. J. Wong, "Comparison of digital offset compensation in comparators," Master's thesis, University of California, Los Angeles, 2002.

H. Jeon, "Low-power high -speed low-offset fully dynamic CMOS latched comparator," Master's thesis, Northeastern Univ., 2010.

R. Baker, I. of Electrical, E. Engineers, and I. S.-S. C. Society, CMOS: Circuit Design, Layout, and Simulation, ser. IEEE Press Series on Microelectronic Systems. John Wiley Sons 2008. [Online].

J. He, S. Zhan, D. Chen, and R. Geiger, "Analyses of static and dynamic random offset voltages in dynamic comparators," Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 56, no. 5, pp. 911-919, May 2009.

Fan, H., Lei, P., Yang, J. et al. "A high-efficient dynamic comparator with low-offset in weak inversion region." Analog Integr Circ Sig Process 110, 175-183 (2022).

Y. Lin, D. Chen, and R. Geiger, "Yield enhancement with optimal area allocation for ratio-critical analog circuits," Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 53, no. 3, pp. 534-553, March 2006.

P. Drennan and C. McAndrew, "Understanding mosfet mismatch for analog design," Solid-State Circuits, IEEE Journal of, vol. 38, no. 3, pp. 450-456, March 2002.

K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, "Characterization and modeling of mismatch in mos transistors for precision analog design," Solid-State Circuits, IEEE Journal of, vol. 21, no. 6, pp. 1057-1066, 1986.

F. N. Zghoul, S. U. Ay, and A. Ababneh, "Gain and offset analysis of comparator using the bisection theorem and a balanced method," International Journal of Electronics, vol. 103, no. 12, pp. 1965- 1983, 2016. [Online].

I. Mehr and D. Dalton, "A 500-msample/s, 6-bit nyquist-rate adc for disk-drive read-channel applications," IEEE Journal of Solid-State Circuits, vol. 34, no. 7, pp. 912-920, Jul 1999.

J. Spalding and D. Dalton, "A 200m sample/s 6b flash adc in 0.6µm cmos," in Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International, Feb 1996, pp. 320-321.

C. C. Enz and G. C. Temes, "Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization," Proceedings of the IEEE, vol. 84, no. 11, pp. 1584-1614, Nov 1996.

Laypeople, "High Speed Comparator Design for the Implementation of Successive Approximation Register ADC," 2019 3rd International Symposium on Multidisciplinary Studies and Innovative Technologies (ISMSIT), 2019, pp. 1-4.

O. A. Hafiz, X. Wang, P. J. Hurst, and S. H. Lewis, "Immediate calibration of operational amplifier gain error in pipelined adcs using extended correlated double sampling," IEEE Journal of Solid-State Circuits, vol. 48, no. 3, pp. 749-759, March 2013.

C.-C. Huang and J.-T. Wu, "A background comparator calibration technique for flash analog-to-digital converters," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 9, pp. 1732-1740, Sept 2005.

C. Donovan and M. P. Flynn, "A "digital" 6-bit adc in 0.25−µm cmos," IEEE Journal of Solid-State Circuits, vol. 37, no. 3, pp. 432-437, Mar 2002.

M. Yoo, Y. Kwon, H. Kim, G. Choi, K. Nam and H. Ko, "Low-Noise Resistive Bridge Sensor Analog Front-End Using Chopper-Stabilized Multipath Current Feedback Instrumentation Amplifier and Automatic Offset Cancellation Loop," in IEEE Access, vol. 10, pp. 12385-12394, 2022.

M. Choi and A. A. Abidi, "A 6-b 1.3-gsample/s a/d converter in 0.35 − µm cmos," IEEE Journal of Solid-State Circuits, vol. 36, no. 12, pp. 1847-1858, Dec 2001.

K. Kattmann and J. Barrow, "A technique for reducing differential non-linearity errors in flash a/d converters," in Solid-State Circuits Conference, 1991. Digest of Technical Papers. 38th ISSCC., 1991 IEEE International, Feb 1991, pp. 170-171.

Y. L. Wong, M. H. Cohen, and P. A. Abshire, "A floating-gate comparator with automatic offset adaptation for 10-bit data conversion," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 7, pp. 1316-1326, July 2005.

M. Miyahara and A. Matsuzawa, "A low-offset latched comparator using zero-static power dynamic offset cancellation technique," in Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian, Nov 2009, pp. 233-236.

R. Ghasemi and M. A. Karami, "A low-power high-speed two-stage dynamic comparator with a new offset cancellation technique in 90 nm CMOS technology," 2020 28th Iranian Conference on Electrical Engineering (ICEE), 2020, pp. 1-6.

Y. Jung, S. Lee, J. Chae, and G. C. Temes, "Low-power and low-offset comparator using latch load," Electronics Letters, vol. 47, no. 3, pp. 167-168, February 2011.

J. Lu and J. Holleman, "A low-power dynamic comparator with timedomain bulk-driven offset cancellation," in 2012 IEEE International Symposium on Circuits and Systems, May 2012, pp. 2493-2496.

J. Lu and J. Holliman, "A low-power high-precision comparator with time-domain bulk-tuned offset cancellation," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 5, pp. 1158-1167, May 2013.

J. Ceballos, I. Galton, and G. Temes, "Stochastic analog-to-digital conversion," in Circuits and Systems, 2005. 48th Midwest Symposium on, Aug 2005, pp. 855-858 Vol. 1.

T. Nguyen, "Robust data-optimized stochastic analog-to-digital converters," Signal Processing, IEEE Transactions on, vol. 55, no. 6, pp. 2735- 2740, June 2007.

S. Weaver, B. Hershberg, D. Knierim, and U.-K. Moon, "A 6b stochastic flash analog-to-digital converter without calibration or reference ladder," in Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian, Nov 2008, pp. 373-376.

S. Weaver, B. Hershberg, P. Kurahashi, D. Knierim, and U.-K. Moon, "Stochastic flash analog-to-digital conversion," Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 57, no. 11, pp. 2825-2833, Nov 2010.

S. Weaver, B. Hershberg, and U.-K. Moon, "Pdf folding for stochastic flash adcs," in Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on, Dec 2010, pp. 770-773.

S. Weaver, B. Hershberg, and U.-K. Moonn, "Digitally synthesized stochastic flash adc using only standard digital cells," in VLSI Circuits (VLSIC), 2011 Symposium on, June 2011, pp. 266-267. 28

S. Weaver, B. Hershberg, and U.-K. Moon, "Digitally synthesized stochastic flash adc using only standard digital cells," Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 61, no. 1, pp. 84-91, Jan 2014.

H. Ham, T. Matsuoka, J. Wang, and K. Taniguchi, "Design of a highspeed-sampling stochastic flash analog-to-digital converter using device mismatch," Electronics and Communications in Japan, vol. 96, no. 1, pp. 51-62, 2013.

A. Waters, S. Leuenberger, F. Farahbakhshian, and U.-K. Moon, "Analysis and performance trade-offs of linearity calibration for stochastic adcs," in Electronics, Circuits and Systems (ICECS), 2014 21st IEEE International Conf. on, Dec 2014, pp. 207-210.

A. Fahmy, J. Liu, T. Kim, and N. Maghari, "An all-digital scalable and reconfigurable wide-input range stochastic adc using only standard cells," Circuits and Systems II: Express Briefs, IEEE Transactions on , vol. 62, no. 8, pp. 731-735, Aug 2015.

Z. Xu, B. Hu, T. Wu, Y. Yao, Y. Chen, J. Ren, and S. Ma, "A 12-bit 50 ms/s split-cdac-based sar adc integrating input programmable gain amplifier and reference voltage buffer," Electronics, vol. 11, no. 12, 2022. [Online].

S. Uto and K. Ohhata, "Stochastic Subranging ADC Using Variable Comparator Offset Technique," 2020 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2020, pp. 232-234.

Xuncheng ZOU, Shigetoshi NAKATAKE, A Low Voltage Stochastic Flash ADC without Comparator, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2019, Volume E102.A, Issue 7, Pages 886-893, Released on J-STAGE July 01, 2019.

F. Frazzica, T. Yasue, A. Spagnolo, D. S. S. Bello, M. De Bock, J. Craninckx, and P. Wambacq, "A 12 bit 4.7-ms/s 260.5- µw digital feedforward incremental-
δσ-sar adc in 0.13-µm cmos for image sensors," IEEE Sensors Journal, vol. 21, no. 19, pp. 21 653-21 666, 2021.

X. Tong, W. Jin, C. Zhang, X. Xin, S. Dong, and Q. Li, "A 0.6-v 12-bit 13.2-fj/conversion-step sar adc with time-domain vcdl-based comparator and metastability immunity technique," Microelectronics Journal, vol. 122, p. 105406, 2022. [Online].

J. Lim, H. Kim, T. N. Jackson, K. Choi, and D. Kenny, "An ultracompact and low-power oven- controlled crystal oscillator design for precision timing applications," IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, vol. 57, no. 9, pp. 1906-1914, September 2010.


  • There are currently no refbacks.

Please send any question about this web site to
Copyright © 2005-2023 Praise Worthy Prize