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A 12-bit Fine-Coarse Successive Approximation Stochastic Analog to Digital Converter
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DOI: https://doi.org/10.15866/irecap.v12i3.22249
Abstract
The surrounding world is composed of continuous time and amplitude analog signals, such as the sound signal picked by a microphone, the light entering a camera, the temperature measured by a thermocouple. In order to process these real world signals by computers, they have to be converted to digital signals. Rapid advances in media technology require high performance analog to digital converters ADCs. In this work, a 12-bit Successive Approximation Register SAR Stochastic Analog to Digital Converter ADC topology has been designed using complementary metal-oxide-semiconductor CMOS in a 0.35µm technology and a single supply voltage equal to 3.3V. In order to reduce the number conversion loops in a typical SAR ADC. 8-bits of the conversion are performed using the SAR ADC and the remainder is fed to the stochastic ADC. Taking the remainder from the SAR ADC allows the input signal of the stochastic ADC to fall within a limited range. The stochastic ADC performs 4-bit conversion using 512 parallel comparators. Since a large number of comparator is used, a simple single ended comparator has been proposed. The proposed comparator reduces the dissipated power by 38% compared to the conventional single ended comparators for each comparator. The gain of the proposed comparator has doubled compared to the conventional single ended comparator. Using this hybrid conversion also solves the problem of the limited input range for stochastic ADCs. Typical stochastic ADCs have an input range around 1mV, using a SAR ADC in the first stage increased the input voltage range to 3.3 V. The ADC has a sample rate of 50Ms/s. The proposed ADC achieves an SNDR equal to 71.2 dB. The DNL -0.44/+0.47 and INL -0.55/+0.59 LSB.
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References
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