Implementation of Low-Power Adaptive Viterbi Decoder for Wireless Communication

Abstract

There has been a surge of research activities in the field of wireless communication which sweep of the communications industry over the few past decades. This has prone to the emerging technologies for effective communication over wireless channels. The need of data transmission rate was increased by shutting the door of noise. Thus the effects of noise in digital data transmission are reduced drastically by the use of error-detecting and correcting convolutional codes. In this paper, the decoding techniques for convolutional codes, Viterbi algorithm, and adaptive Viterbi algorithm which is based on strongly connected trellis was proposed. The Viterbi algorithm achieves its optimum performance in BER. The low power design technique, Adaptive Viterbi algorithm is applied to the decoder design to improve its power efficiency. This adaptive technique has been implemented on a FPGA and demonstrates a significant power saving at low noise levels. Viterbi decoder and adaptive Viterbi decoder was compared in terms of BER performance, which are also developed in MATLAB and FPGA. The proposed algorithm reduces the average number of ACS computations up to 70% compared to normal Viterbi algorithm, with the same BER performance. Also the improvement in BER performance was compared for different constraint lengths.
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