Open Access Open Access  Restricted Access Subscription or Fee Access

Optimization and Implementation of Acoustic Echo Canceller Based on LMS Algorithm Using FPGA

(*) Corresponding author

Authors' affiliations



Acoustic echo is a major problem in voice communication system. It reduces significantly the quality of the signal at the far-end user side. To overcome this problem, the use of Acoustic Echo Canceller (AEC) is unavoidable. This paper presents the implementation of an acoustic echo canceller with long room impulse response of 128 taps modeling real room characteristics using fixed step size least mean square (LMS) algorithm. The floating-to-fixed point conversion of the AEC was optimized by performing different Matlab simulations to reduce the hardware resources and the power consumption while maintaining the expected performance. The Register Transfer Level (RTL) description of the designed AEC is then simulated and synthesized, using ISim from Xilinx, for the target device FPGAVirtex-6 XC6VLX240T. Simulation results proved that optimized fixed-point architecture gives the same performance in terms of convergence rate and steady-state mean square error obtained with floating-point architecture.
Copyright © 2014 Praise Worthy Prize - All rights reserved.


Acoustic Echo Canceller; Adaptive Filter; Least Mean Squares (LMS); Fixed Point Optimization; FPGA

Full Text:



S.V. Vaseghi, Dsp - Advanced Digital Signal Processing And Noise Reduction (John Wiley Sons, 2008).

A.M. Nassar, A.M Ali, A New Technique of Modeling Acoustic Echo and its Implementation Using FPGA, Japan-China Joint Workshop FCST,IEEE, 2008.

Karjalainen, Matti and Esquef, P. A. Andrade and Antsalo, Poju and Makivirta, Aki and Valimaki, Vesa, AR/ARMA Analysis and Modeling of Modes in Resonant and Reverberant Systems, Audio Engineering Society Convention 112, April 2002.

S. Haykin, Adaptive Filter Theory (Fourth Edition, PrenticeHall, Upper Saddle River, N.J., 2002).

M.M. Sondhi, An Adaptive Echo Canceller, Bell Syst. Tech. J., vol. 46, No.3, pp. 497-511, Mar. 1967.

A. Sharma1, Y.Juneja, Acoustic Echo Cancellation from the Signal Using LMS Algorithm, International Journal of Research in Advent Technology, Vol.2, No.6, June 2014.

Su An Jang ; You Jin Lee ; Dai Tchul Moon, Design and Implementation of an Acoustic Echo Canceller, ASIC,. Proceedings. IEEE Asia-Pacific Conference on, 2002.

E. Abdel-Raheem, On Computationally Efficient NLMS-Based Algorithms for Echo Cancellation Applications, International Symposium on Signal Processing and Information Technology, IEEE 2005.

J. Dai, Y. Wang, NLMS Adaptive Algorithm Implement Based on FPGA, ASIC,Third International Conference on Intelligent Networks and Intelligent Systems, IEEE 2010.

M.N.Mohanty, B.Mishra, A.Routray, FPGA implementation of constrained LMS algorithm, Energy, Automation, and Signal (ICEAS), 2011 International Conference on, IEEE 2011.

J.Jian ; G.Yuantao ; M.Shunliang, SparseConstraint Multidelay Frequency Adaptive FilteringAlgorithm for Echo Cancellation, Audio Language and Image Processing (ICALIP), IEEE 2010.

W.Shenming, W. Suntiamorntut,N. Jindapetch, Scheduling & Resources Sharing Technique for Adaptive LMS Filter, The 8thElectrical EngineeringElectronics, Computer, Telecommunications and Information Technology (ECTI), Association of Thailand, IEEE 2011.

Alaeddine, H.H., Beydoun, A., Beydoun, B., Khalil, F., Rachini, A., A novel double talk echo canceller algorithm using multi delay filter, (2013) International Journal on Communications Antenna and Propagation (IRECAP), 3 (4), pp. 199-205.

C. Paleologu, S. Ciochina, and J. Benesty, Double talk robust VSS-NLMS algorithm for under-modeling acoustic echo cancellation, Proc. ICASSP, pp. 245–248, March, IEEE 2008.

M. Salah, A. Zekry, M.Kamel, FPGA Implementation of LMS Adaptive Filter, 28th NATIONAL RADIO SCIENCE CONFERENCE (NRSC 2011), National Telecommunication Institute, Egypt, April 26-28, 2011.

A.Elhossini, S.Areibi,An FPGA Implementation of the LMS Adaptive Filter for Audio Processing, International Conference onReconfigurable Computing and FPGA's, ReConFig, IEEE 2006.

K. Kum and W. Sung, Combined word-length optimization and highlevel synthesis of digital signal processing systems, TCAD, vol. 20,no. 8, IEEE 2001.

K. Han and B.L. Evans, Optimum Wordlength Search Using Sensitivity Information, EURASIP Journal on ASP, vol. 2006, pp. 1-14, 2006.

C. Roth, Digital System Design Using VHDL (Jr PWS Publication Company,1998).

V. A.Pedroni, Circuit Design with VHDL (MIT Press 2004).


  • There are currently no refbacks.

Please send any question about this web site to
Copyright © 2005-2024 Praise Worthy Prize