An Intelligent Speed Limit Sign Recognition Approach Towards an Embedded Driver Assistance System
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Road traffic safety has become a significant global public health issue. The number of traffic crashes is increasing in alarming proportions, leading to a large number of deaths and injuries. Most road accidents occur due to human errors including exceeding speed limit and failure to abide by driving rules. Therefore, in order to solve this issue, advanced driver-assistance systems are more and more in use thanks to their capabilities in minimizing the human error. These systems are used to enhance or adapt some or all of the tasks involved in operating a vehicle. Designers rely heavily on Artificial Intelligence in order to operate these systems. In this framework, this paper discusses the development of an intelligent speed limit signs’ recognition system, which can substantially enhance road safety. Since this system is conceived to be implanted on an FPGA card, the main challenges consist in achieving a high recognition rate with a low complexity level in the proposed algorithm. This will undoubtedly lead up to an optimized hardware architecture suitable for real time processing. For this purpose, a two-step based vision speed limit signs’ detection and recognition system has been proposed. The first step concerns sign candidate’s detection based on color and shape analysis; it consists in different sub image processing levels. The second step deals with the recognition and identification of the detected signs. To this end, several Machine Learning algorithms and several architectures of multilayer Neural Network and Wavelet Neural Network have been evaluated. The analysis of performance results and comparison with other widely used techniques have shown the effectiveness and efficiency of the proposed technique in terms of percentage of correct classification and execution time even for images captured under varied orientations and varied illumination conditions.
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