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Analysis of Miller Capacitance in Si Tunnel Field-Effect Transistors and Potential for Low-Voltage/Low-Energy Applications

Yuyang Jiang(1), Shingo Sato(2), Yasuhisa Omura(3*), Abhijit Mallik(4)

(1) Kansai University, Japan
(2) Kansai University, Japan
(3) Kansai University, Japan
(4) University of Calcutta, India
(*) Corresponding author


DOI: https://doi.org/10.15866/irea.v7i3.17027

Abstract


The purpose of this paper is to analyze the reason why the gate-to-drain capacitance (Miller capacitance) of a tunnel FET (TFET) is very large, and to reveal key aspects of the capacitance components of TFET. A numerical device simulator is used to compare lateral and vertical TFET performance. It is demonstrated that the Miller capacitance of the devices, particularly the lateral TFET, can be drastically reduced without degrading the drivability, by using gate-to-drain off-set. It is also demonstrated that while vertical TFETs are promising for decreasing the switching delay, they suffer the fatal demerit of poor drivability when scaled.  In addition, this paper tackles the numerical modelling of TFET capacitance components in order to appropriately estimate switching delay time of the devices; no reliable model has been proposed for TFETs to date.  It is shown that the capacitance model leads to better estimates of switching delay times of TFETs than the conventional estimation method.
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Keywords


Lateral TFET; Vertical TFET; Parasitic Capacitance; Miller Capacitance; Gate-Drain Offset; Switching Performance

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References


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