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Analysis of Miller Capacitance in Si Tunnel Field-Effect Transistors and Potential for Low-Voltage/Low-Energy Applications

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The purpose of this paper is to analyze the reason why the gate-to-drain capacitance (Miller capacitance) of a tunnel FET (TFET) is very large, and to reveal key aspects of the capacitance components of TFET. A numerical device simulator is used to compare lateral and vertical TFET performance. It is demonstrated that the Miller capacitance of the devices, particularly the lateral TFET, can be drastically reduced without degrading the drivability, by using gate-to-drain off-set. It is also demonstrated that while vertical TFETs are promising for decreasing the switching delay, they suffer the fatal demerit of poor drivability when scaled.  In addition, this paper tackles the numerical modelling of TFET capacitance components in order to appropriately estimate switching delay time of the devices; no reliable model has been proposed for TFETs to date.  It is shown that the capacitance model leads to better estimates of switching delay times of TFETs than the conventional estimation method.
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Lateral TFET; Vertical TFET; Parasitic Capacitance; Miller Capacitance; Gate-Drain Offset; Switching Performance

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K. Gopalakrishnan, R. Woo, C. Jungemann, P. B. Griffin, and J. D. Plummer, Impact ionization MOS (I-MOS)-Part II: experimental results, IEEE Trans. Electron Devices, vol. 52, 2005, pp. 77-84.

Q. Zhang, W. Zhao, and A. Seabaugh, Low-Subthreshold-Swing Tunnel Transistors, IEEE Electron Devices Lett., vol. 27, 2006, pp. 297-300.

A. C. Seabaugh and Q. Zhang, Low-Voltage Tunnel Transistors for Beyond CMOS Logic, Proc. IEEE, vol. 98, 2010, pp. 2095-2110.

K. Tomioka and M. Yoshimura, and T. Fukui, Steep-Slope Tunnel Field-Effect Transistors Using III-V Nanowire/Si Heterojunction, Tech. Dig. Symp. VLSI Technol., June, 2012, Kyoto, Japan.

L. Knoll, Q. T. Zhao, S. Trellenkamp, A. Schfer, K. K. Bourdelle, and S. Mantl, Si tunneling transistors with high on-currents and slopes of 50 mV/dec using segregation doped NiSi2 tunnel junctions, Proc. European Solid State Device Research Conference ~ESSDERC~, Sep. 2012, Bordeaux, France.

A. Villalon, C. L. Royer, M. Cassé, D. Cooper, J.-M. Hartmann, F. Allain, C. Tabone, F. Andrieu, and S. Cristoloveanu, Experimental Investigation of the Tunneling Injection Boosters for Enhanced Ion ETSOI Tunnel FET, IEEE Trans. Electron Devices, vol. 60, 2013, pp. 4079-4084.

C. Alper, P. Palestri, J. L. Padilla, and A. M. Ionescu, The Electron-Hole Bilayer TFET: Dimensionality Effects and Optimization, IEEE Trans. Electron Devices, vol. 63, 2016, pp. 2603-2608.

R. Jhaveri, V. Nagavarapu, and J.C. Woo, Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor, IEEE Trans. Electron Devices, Vol. 58, 2011, pp. 80-86.

U. Avci, D. H. Morris, I. A. Young, Tunnel field-effect transistors: prospects and challenges, IEEE J. Electron Device Soc. Vol. 3, 2015, pp. 88-95.

J. Knoch, S. Mantl, and J. Appenzeller, Impact of the dimensionality on the performance of tunneling FETs: Bulk versus one-dimensional devices, Solid State Electron., vol. 51, 2007, pp. 572-578.

S. Agarwal and E. Yablonovitch, Using dimensionality to achieve a sharp tunneling FET (TFET) turn-on, Abstr. IEEE Device Research. Conference ~DRC~, June, 2011, Santa Barbara, CA, USA.

S. Agarwal, Reinventing the PN junction: Dimensionality Effects on Tunneling Switches, Ph. D. Dissertation (Electrical Eng. and Comp. Sci. University of California at Berkeley, Technical Report No. UCB/EECS-2012-97. May 11, 2012.

Y. Taur, J. Wu, and J. Min, Dimensionality dependence of TFET performance down to 0.1 V supply voltage, IEEE Trans. Electron Devices, vol. 63, 2016, pp. 877-880.

Y. Omura, Two-Dimensional Quantization Effect on Indirect Tunneling in an Insulated-Gate Lateral pn-Junction Structure with a Thin Silicon Layer, Jpn. J. Appl. Phys., Vol. 39, 2000, pp. 1597-1603.

Y. Omura, Experimental Study of Two-Dimensional Confinement Effects on Reverse-Biased Current Characteristics of Ultra-Thin Silicon-on-Insulator (SOI) Lateral, Unidirectional, Bipolar-Type Insulated-Gate Transistors (Lubistors), Jpn. J. Appl. Phys., vol. 46, 2007, pp. 2968-2972.

T. Hoehr, A. Schenk and W. Fichtner, Revised Shockley–Read–Hall lifetimes for quantum transport modeling, J. Appl. Phys., vol. 95, 2004, pp. 4875-4882.

H. Nii, T. Yamada, K. Inoh, and Y. Katsumata, A Novel Lateral Bipolar Transistor with 67GHz f-max on Thin Film SOI for RF Analog Applications, IEEE Trans. Electron Devices, vol. 47, 2000, pp. 1536-1541.

T. H. Ning, A Perspective on SOI Symmetric Lateral Bipolar Transistors for Ultra-Low-Power Systems, IEEE J. Electron Device Soc., vol. 4, 2016, pp. 227-235.

S. Mookerjea, R. Krishnan, S. Datta, and V. Narayanan, Effective Capacitance and Drive Current for Tunnel FET (TFET) CV/I Estimation, IEEE Trans. Electron Devices, vol. 56, 2009, pp. 2092-2098.

Y. Yang, X. Tong, L.-T. Yang, P.-F. Guo, L. Fan, and Y.-C. Yeo, Tunneling Field-Effect Transistor: Capacitance Components and Modeling, IEEE Electron Device Lett., vol. 31, 2010, pp. 752-754.

C. Alper, L. D. Michielis, N. Dagtekin, L. Lattanzio, and A. M. Ionescu, Tunnel FET with Non-Uniform Gate Capacitance for Improved Device and Circuit Level Performance, Proc. European Solid State Devices Research Conference ~ESSDERC~, Sep. 2012, Bordeaux, France.

D. Woong, J. H. Kim, and B.-G. Park, Effects of Drain Doping Concentration on Switching Characteristics of Tunnel Field-Effect Transistor Inverters, Jpn. J. App. Phys., vol. 55, 2016, pp. 114201.

Y. Jiang, S. Sato, Y. Omura, and A. Mallik, Aspects and Reduction of Miller Capacitance of Lateral Tunnel FET, Abstr., IEEE International Meeting for Future Electron Devices, Kansai ~IMFEDK~, June, 2018, Kyoto, Japan.

R. H. Olsson, Radoslav B. Bogoslovov, Christal Gordon, Event driven persistent sensing: Overcoming the energy and lifetime limitations in unattended wireless sensors, Proc. IEEE Sensors, Nov., 2016, Florida, USA.

Y. Mori, S. Sato, Y. Omura, A. Chattopadhyay and A. Mallik, On the Definition of Threshold Voltage for Tunnel FETs, Superlat. And Microstruct., vol. 107, pp. 17-27, 2017.

A. Mallik, A. Chattopadhyay, S. Guin, and A. Karmakar, Impact of a spacer-drain overlap on the characteristics of a silicon tunnel field-effect transistor based on vertical tunneling, IEEE Trans. Electron Devices, vol. 60,2013, pp. 935-943.

Sentaurus Operations Manual (Synopsys, 2010).

G. Kim, J. Lee, J. H. Kim, and S. Kim, High On-Current Ge-Channel Heterojunction Tunnel Field-Effect Transistor Using Direct Band-to-Band Tunneling, MDPI Micromachines, vol. 2019, 2019, pp. 1-8.

D. Navarro, N. Nakayama, K. Machida, Y. Takeda, S. Chiba, H. Ueno, H. J. Mattausch, M. Miura-Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, and S. Miyamoto, Modeling for Carrier Transport Dynamics at GHz-Frequencies for RF Circuit-Simulation, Proc. International Conference Simulation Semiconductor Processes & Devices ~SISPAD~, Sept. 2004, Munich, Germany.

D. Navarro, N. Nakayama, K. Machida, Y. Takeda, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, and S. Miyamoto, A Carrier Transit Time Delay-Based Non-Quasi-Static MOSFET Model for RF Circuit Simulation, The 2nd International Workshop on Compact Modeling, ~IWCM~, May, 2005, Anaheim, Germany.

L. Chang. D. J. Frank, R. K. Montoye, S. J. Koester, B. L. Ji, P. W. Coteus, R. H. Dennard, and W.Haensch, Practical Strategies for Power-Efficient Computing Technologies, Proc. IEEE, vol. 98, 2010, pp. 215-236.

S. Vitale, P. W. Wyatt, N. Checka, J. Kedzierski, and C. L. Keast,, FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics, Proc. IEEE, vol. 98, 2010, pp. 333-342.

F. Chen, H. Ilatikhamench, Y. Tan, G. Klimeck, and R. Rahman, Switching Mechanism and the Scalability of vertical-TFETs, arXiv: 1711.01832v3 [cond-mat.mtrl-sci] 3 Dec 2017.

Yuyang Jiang, Studies on Drain-Current Modelling and Switching Characteristic of Vertical Tunnel FET, Ms. Degree Thesis, Kansai University, Feb., 2019.

H. Veendrick, Deep-Submicron CMOS ICs, 2nd Ed. (Kluwer Academic Pub., 2000, Chapter 4).


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