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Design of High-Performance All-Digital Clock Recovery Circuit Requiring Short Preamble Data
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Abstract
This paper describes the architecture and design of a hybrid all-digital clock recovery circuit. The proposed clock recovery circuit is designed in a fully digital style in order to provide better scalability and portability. The proposed circuit is a hybrid since it operates coherently with an analog-to-digital converter (ADC). The final clock is determined by minimizing the discrepancies between the preambles sampled by the ADC and the expected ones. The number of the required preamble data is smaller than other approaches because simple and efficient search algorithms are used to determine the final clock with the most appropriate phase. The proposed hybrid clock recovery circuit is designed using 130nm, 1.2V CMOS technology and simulated with 1.1Gb/s incoming preambles using HSpice circuit simulator. The measured jitter tolerance against the input jitter is a 33% unit interval (UI). The number of the required preamble data in our circuit is 13
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References
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